2017
[1] H. Bauer, S. Höppner, J. Partzsch, D. Walter, C. Mayr, F. Schraut and H. Eisenreich. Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. In IEEE Nordic Circuits and Systems Conference (NORCAS), IEEE, 2017.
[2] S. Haas, S. Scholze, S. Höppner, A. Ungethüm, C. Mayr, R. Schüffny, W. Lehner and G. Fettweis. Application-specific architectures for energy-efficient database query processing and optimization. Microprocessors and Microsystems, 55:119-130, Elsevier, 2017.
[3] S. Haas, T. Seifert, B. Nöthen, S. Scholze, S. Höppner, A. Dixius, E. Adeva, T. Augustin, F. Pauls, S. Moriam and others. A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. In Proceedings of the 54th Annual Design Automation Conference 2017, pages 47, 2017.
[4] S. Höppner, Y. Yan, B. Vogginger, A. Dixius, J. Partzsch, F. Neumärker, S. Hartmann, S. Schiefer, S. Scholze, G. Ellguth, L. Cederstroem, M. Eberlein, C. Mayr, S. Temple, L. Plana, J. Garside, S. Davison, D.R. Lester and S.B. Furber. Dynamic Voltage and Frequency Scaling for Neuromorphic Many-Core Systems. In IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2017 (submitted)
[5] H. Keren, J. Partzsch, S. Marom and C. Mayr. Closed-loop control of a modular neuromorphic biohybrid. PLOS Computational Biology, 2017 (submitted)
[6] M. Raitza, A. Kumar, M. Völp, D. Walter, J. Trommer, T. Mikolajick and W.M. Weber. Exploiting transistor-level reconfiguration to optimize combinational circuits. In Design, Automation Test in Europe Conference Exhibition (DATE), pages 338-343, IEEE, 2017.
[7] J. Partzsch, S. Höppner, M. Eberlein, R. Schüffny, C. Mayr, D.R. Lester and S.B. Furber. A Fixed Point Exponential Function Accelerator in 28nm CMOS for a Digital Neuromorphic System. In IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2017. (submitted)
[8] M.A. Petrovici, S. Schmitt, J. Klähn, D. Stöckel, A. Schroeder, G. Bellec, J. Bill, O. Breitwieser, I. Bytschok, A. Grübl and others. Pattern representation and recognition with accelerated analog neuromorphic systems. arXiv preprint arXiv:1703.06043, 2017.
[9] S. Schmitt, J. Klaehn, G. Bellec, A. Grübl, M. Guettler, A. Hartel, S. Hartmann, D. Husmann, K. Husmann, S. Jeltsch and others. Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system. In Neural Networks (IJCNN), 2017 International Joint Conference on, pages 2227-2234, 2017.
[10] J. Trommer, A. Heinzig, S. Slesazeck, U. Mühle, M. Löffler, D. Walter, C. Mayr, T. Mikolajick and W. Weber. Reconfigurable germanium transistors with low source-drain leakage for secure and energy-efficient doping-free complementary circuits. In Device Research Conference (DRC), 2017 75th Annual, pages 1-2, 2017.
2016 |