Publications
actual, 2023:
| [1] | A. Subramoney, K. Nazeer, M. Schöne, C.G. Mayr and D. Kappel. Efficient recurrent architectures through activity sparsity and sparse back-propagation through time. In The Eleventh International Conference on Learning Representations, 2023 |
| [2] | H. Bauer, M. Stolba, S. Scholze, D. Walter, C. Mayr, A. Oefelein, S. Höppner, A. Scharfe, F. Schraut and H. Eisenreich. A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. In 2023 20th International SoC Design Conference (ISOCC), pages 67-68, 2023 |
| [3] | J. Huang, F. Kelber, B. Vogginger, B. Wu, F. Kreutz, P. Gerhards, D. Scholz, K. Knobloch and C.G. Mayr. Efficient Algorithms for Accelerating Spiking Neural Networks on MAC Array of SpiNNaker 2. In 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023. (accepted) |
| [4] | C. Liu, J. Li, H.A. Gonzalez, B. Vogginger and C. Mayr. Complex-Valued Neural Networks for Doppler Disambiguation in FMCW Radars. In 2023 24th International Radar Symposium (IRS), 2023 |
| [5] | L. Guo, M. Jobst, J. Partzsch, S. Scholze, A. Dixius, M. Lohrmann, S. Zeinolabedin and C. Mayr. A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI. In 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023. (accepted) |
| [6] | F. Schüffny, S. Höppner, S. Hänzsche, R. George, S. Zeinolabedin and C. Mayr. Power Minimization in Neural Recording ΔΣ Modulators by Adaptive Back-Gate Voltage Tuning. IEEE Solid-State Circuits Letters, 2023 |
| [7] | B. Wu, W. Furtner, B. Waschneck and C.G. Mayr. Prototyping of Low-Cost Configurable Sparse Neural Processing Unit with Buffer and Mixed-Precision Reshapeable MAC Array. In 2022 IEEE 28th International Conference on Parallel and Distributed Systems (ICPADS), ():712-719, 2023 |