Topics for Student Theses

Entwurf und Analyse von Radarsystemen

Gruppenleiter: Dr.-Ing. Niko Joram

  • Extension of a FMCW primary radar system based on off-the-shelf components regarding implementing the receiving path (SA/BA/PA) (M. Gunia) - NEW 03/2021
    • Familiarization with FMCW, the already available sending path (PLL - filter - VCO) and research on receiving architectures.
    • Design of the receiving path based on off-the-shelf components, PCB design and test.
  • Design of an accurate positioning system by means of the Channel State Information (CSI) of commercial WiFi network cards (SA/BA/PA) (M. Gunia)

    Sub tasks:
    • Putting a Linux base station into operation with the help of the Intel 5300 chips
    • Implementation of Angle-of-Arrival Ansatzes by means of the MUSIC algorithm
  • Comparison of the Angle of Arrival based positioning system, developed at the chair, with respect to a commercial system, designed by the company Metirionic (SA/BA/PA) (M. Gunia)

    Sub tasks:
    • Becoming acquainted with both systems (the work will be conducted in close cooperation with Metirionic).
    • Comparison of both systems with respect to possible improvements.

  • Feature recognition with broadband FMCW radar (SA/DA/MA) (B. Al-Qudsi)

  • Optimum FSK receiver for coarse time synchronization (DA/MA) (B. Al-Qudsi)

  • Analyse und Entwurf eines digital gesteuerten Ultrabreitband-Oszillators (DCO) zur Verwendung innerhalb einer ADPLL (SA/DA)  (T. Drechsel)
  • From One-Way lane to a Two-Way Freeway : Analysis and Design of 60 GHz Quasi Circulators in 22 nm FD SOI for Full Duplex RFID Systems (MA/DA/SA) (M.V. Thayyil )

  • Design of a  60-GHz FMCW radar frontend demonstrator. (SA/DA/MA) (Y. Zhu)

  • Analysis and design of a 60-GHz injection-locked frequency tripler for radar transceivers (SA/DA/MA)(Y. Zhu)

  • Entwicklung eines echtzeitfähigen Algorithmus zur Unterdrückung von Störeinflüssen in einem maritimen FMCW MIMO Radar. (DA/MA/SA) (A. Figueroa)

    • Python/C(++)-Implementierung eines Algorithmus zur Störunterdrückung

    • Verwendung von CUDA und/oder Mehrkernberechnungen zur Parallelisierung

  • Analysis and Design of 60 GHz N-path filters in 22 nm FD SOI for Full Duplex RFID Systems (MA/DA/SA) (M.V. Thayyil )

  • Development of STM32 firmware with focus on sleep/wakeup behavior and data processing for an wireless implant module (SHK) ( M. Becker)

Schaltungen und Komponenten zur optischen Datenübertragung

Gruppenleiter: Dr. Ronny Henker

  • Investigation and simulation of on-chip transformers with full 3D EM simulation tool. (SA, project work) (G. Belfiore)
  • Investigation and simulation of equalization techniques for duobinary optical transceivers. (DA, MA) (G. Belfiore)
  • Mismatch compensation in a multi-channel track & hold network of a high-speed time-interleaved ADC in 22 nm CMOS / Mismatchkompensation eines mehrkanaligen Folge-Halte-Netwerks bei zeitversetzt-abtastenden ADCs in der 22 nm CMOS-Technologie (DA) (J. Pliva)
  • Design of a scalable multi-channel time-interleaved FIFO register with SPI interface for data capturing in time-interleaved ADCs. / Entwurf eines skalierbaren mehrkanaligen zeitversetzt getasteten FIFO-Registers mit SPI Schnittstelle zur Datenerfassung in zeitversetzt abtastenden AD-Wandlern. (SA) (J. Pliva)
  • Design and layout of an offset-compensated strong-ARM latch comparator and design study of a SAR-ADC with 6b-resolution and sampling rate in GS/s range. / Entwurf und Layout eines offsetkompensierten Komparators in der strong-ARM Topologie und Studie eines SAR-ADCs mit 6-Bit und Abtastrate in GS/s-Bereich. (DA) (J. Pliva)
  • Analysis, design and simulation of a high speed (25 Gbit/s and beyond) modulator driver in 250 nm BiCMOS technology. (SA) (A. Giuglea)

  • Design of a common-anode VCSEL driver with 3-tap feed-forward equalizer (MA/DA) (130 nm BiCMOS or 22 nm SOI CMOS) (M. Khafaji) 

  • Analysis and design of transimpedance amplifier (TIA) design for optical communications (SHK/MA/DA) (130 nm BiCMOS) (M. Khafaji) 

    • Like to do math for linear circuits and probably work on Volterra series analysis

    • A grade higher than 1.7 in Schaltungstechnik OR a grade higher than 1.3 in RFIC/ICBC

Nanoelektronische Schaltungstechnik

Gruppenleiter: Dr.‐Ing. Corrado Carta

Schaltungen und Systeme in neuartiger Elektronik

Gruppenleiter: Dr.‐Ing. Corrado Carta

Organic and Bio-electronics

Gruppenleiter: Dr.-Ing. Bahman K. Boroujeni

  • Electromagnetic simulation and electrical measurement of 3D organic structures, using EMPro and ADS software. Master thesis, DA, or project work. Please contact Dr.-Ing. Bahman K. Boroujeni for more details.

Entwurf von Komponenten für drahtlose Datenübertragung

Gruppenleiter: Dr.‐Ing. Jens Wagner

  • Entwurf eines Power-Detectors für einen Wake-Up Empfänger in 22 nm SOI CMOS (SA/DA) (B. Lindner)
  • Entwurf eines Komparators für einen Wake-Up Empfänger in 22 nm SOI CMOS (SA/DA) (B. Lindner)
  • Analysis and design of a power amplifier in 130nm SiGe with high efficiency and high output power at 3.6 GHz (SA/DA/MA). (A. Seidel)
  • Analysis and design of a discrete Class J power amplifier in GaN (SA/PW). (A. Seidel)
  • Analysis and implementation approaches for polar modulated baseband signals (SA/PW). (A. Seidel)
  • Boot up strategies for coupled oscillator networks (SA/PW/DA/MA) (C. Hoyer)
  • Large Loop-Bandwidth PLL architectures in BiCMOS (SA/PW/DA/MA) (C. Hoyer)
  • Scalable Digital Interface for SPI Communication in BiCMOS (SA/PW) (C. Hoyer)
  • Student for Assembly and Soldering Jobs (SHK) (C. Hoyer)
  • Variable gain amplifier in BiCMOS (SA/PW/DA/MA) (R. Riaz)
  • Analysis and design of a self-organized coupled PLL network including phase-frequency detectors (DA/MA) (R. Riaz)
  • Analysis and design of a voltage controlled delay line in BiCMOS (SA/DA/MA/PW) (R. Riaz)
  • The analysis and design of a phase frequency detector for high operation frequencies i.e 15GHz/7.5GHz in 130nm SiGe BiCMOS technology (R. Riaz)

Schaltungen im Sub-THz-Bereich

Gruppenleiter: Dr.‐Ing. Corrado Carta

  • In the frame of Impulsed Radio Transceivers  operating between 10 GHz -220 GHz, the listed positions are available. Please be aware that some could be taken in the meantime (P. V. Testa). 
    • UWB Pulse Detectors
    • UWB Pulse Generators
    • UWB Radio Link Design
    • Reconfigurable Distributed Amplifier
    • Distributed Mixer Design
  • Analysis and design of a high linearity power amplifier at 77 GHz in 22 nm FDSOI. (DA) (>S. Li)
  • Research and analysis of a transformer based low-loss matching network topology for 77 GHz applications. (SHK/SA) (>S. Li)

  • Measurement setup automation for characterization of an RF oscillator. (SHK) (>A. Ferchichi)

  • Design of a  superregenerative oscillator at 60 GHz. (SA,DA) (>A. Ferchichi)

  • Design of an OOK demodulator at 60 GHz. (SA,DA) (>A. Ferchichi)

  • Design and layout of a 60 GHz power amplifier with high voltage transistors in 22 nm FDSOI (SA,DA)  (>M.Cui)

  • Design and layout of a 15 GHz to 60 GHz frequency quadrupler in 22 nm FDSOI (SA,DA)  (>M.Cui)

  • DE: Analyse und Entwurf eines Linearen CMOS Leistungsdetektor für 60 GHz Anwendungen (SA/DA)
    EN: Analysis and Design of a Linear CMOS Power Detector for 60 GHz Applications (SA/DA)
    Topic summary (Z. Tibenszky)

  • Analyse und Entwurf eines breitbandigen LNAs für 5G Anwendung / analysis and design of a broadband LNA for 5G applications (SA/MA/DA) (Xin Xu)

  • Analyse und Entwurf eines breitbandigen Leistungsverstärkers für 5G Anwendung / analysis and design of a broadband power amplifier for 5G applications (SA/MA/DA) (Xin Xu)

  • Analysis and design of a transformer-based dualband power amplifier for 5G applications (SA/MA/DA) (Xin Xu)

  • Design and Layout of a 245 GHz 365 degree efficient vector modulator/ phase shifter for precise mmWave beam steering. (SA, MA, DA) (L. Steinweg)

  • Design of a 61.25 GHz LO 1:4 power splitter for a reconfigurable transmitter system (SA, MA, DA) (L. Steinweg)

    • Research and design active power splitter circuits

    • Reference design Wilkinson divider

    • Analysis of behavior when switching separate transmitter paths

  • Design and Layout of a Low Noise Distributed Amplifier operating up to 100 GHz with focus of noise reduction. (SA, MA, DA)(H. Morath)
  • Design, simulation and layout of aVoltage Controlled Oscillator for 77 GHz radar in 22nm FDSOI. (MA, DA) (L. Szilagyi)
  • Analysis and design of a low noise amplifier operating at 140GHz in 22 nm FDSOI Technology. (SA,MA,DA)(S.M.Seyyedrezaei)
  • Analysis and design of a 140 GHz passive mixer in 22 nm FDSOI Technology. (SA,MA,DA)(S.M.Seyyedrezaei)

Mixed-Signal Circuit Design

Gruppenleiter: Dipl.‐Ing. Martin Kreißig

  • Analysis and design of a Dickson rectifier for energy harvesting in non-duty-cycled systems. (SA) (R. Ma)

  • Analysis and design of an ultralow-power relaxation oscillator for duty-cycled systems . (SA) (R. Ma)

  • Analysis and design of a 400 MHz low-noise, low-power and fast-switchable bandpass filter with Q-factor enhancement technique for duty-cycled receivers. (SA/DA/MA) (R. Ma)

  • Analysis and design of  RF power combiner structures. Knowledge/experience in PCB design is required. (SHK) (M. Kreißig)
  • Analysis and design of an integrated high voltage current steering DAC for arbitrary waveform generation up to 10MHz (SA/DA/MA) (F. Schwarze)
  • Design, implementation and verification of a mixed-signal filter network for PoDL systems  (SA/DA/MA) ( F. Schwarze)
  • Comparator Based Mixed-Signal Control Loop  (SA) (F.Protze)

Data Converter Design

Gruppenleiter: Dr.-Ing. Mohammad Mahdi Khafaji

  • Design of a high speed serializer for an ADC output interface (SA/DA/MA) (S. Buhr)

  • Design of a high speed single-core analog-to-digital converter (SA/DA/MA) (S. Buhr)

  • Design of a time-interleaved high speed analog-to-digital converter (SA/DA/MA) (S. Buhr)

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Frank Bindrich
Last modified: Apr 08, 2021
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