publications

2012

• On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC LinksHöppner, S., Walter, D., Ellguth, G. & Schüffny, R., 1 Mar 2012, In: International Journal of Embedded and Real-Time Communication Systems (IJERTCS). 3, 4, p. 42-56, 15 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article

2011

• Demo: Waferscale Communication infrastructureMayr, C., Partzsch, J., Scholze, S. & Schüffny, R., 1 Dec 2011, Fet11 - The European Future Technologies Conference and ExhibitionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Design Flow Integration of the Linearized Operating Point (LOP) MethodHöppner, S., Henker, S., Görner, J. & Schüffny, R., 1 Dec 2011, MunEDA User Group MeetingElectronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• IP Porting and Resizing for High-Speed NoC Links from 65nm to 28nm Globalfoundries CMOS Technology with WiCkeDWalter, D., Höppner, S. & Schüffny, R., 1 Dec 2011, MunEDA User Group MeetingElectronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Mismatch Characterization of High-Speed NoC Links using Asynchronous Sub-SamplingHöppner, S., Walter, D., Ellguth, G. & Schüffny, R., 1 Dec 2011, IEEE International Symposium on System on Chip. p. 112-115, 4 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution

2010

• Exploration of Feasible Voltage Ranges in Analog CMOS Circuits Using Linearized-Operating-Point Transistor ModelsHöppner, S., Henker, S., Schüffny, R. & Graupner, A., 1 Dec 2010, MunEDA User Group MeetingElectronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Highly Integrated Packet-Based AER Communication Infrastructure with 3Gevent/s ThroughputHartmann, S., Schiefer, S., Scholze, S., Partzsch, J., Mayr, C., Henker, S. & Schüffny, R., 1 Dec 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems. IEEE Xplore, p. 952-955, 4 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Using neuron dynamics for realistic synaptic learningMayr, C., Partzsch, J., Noack, M. & Schüffny, R., 1 Dec 2010, The Neuromorphic EngineerElectronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Efficient compensation of delay variations in high-speed network-on-chip data linksHöppner, S., Walter, D., Eisenreich, H. & Schüffny, R., 1 Sep 2010, IEEE International Symposium on System on Chip (SoC). p. 55-58, 4 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Low Power Design of the X-GOLD® SDR 20 Baseband ProcessorRaab, W., Berthold, J., Hachmann, U., Langen, D., Schreiner, M., Eisenreich, H., Schlüßler, J. & 1 others, 1 Mar 2010, Proceedings of Design, Automation and Test in Europe (DATE 2010)Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution