publications

2007

• Nearest Neighborhood Greyscale Operator for hardware-efficient micro-scale texture extractionMayr, C. & König, A., 1 Dec 2007, In: EURASIP journal on advances in signal processing. Vol. 2007, p. Article ID 52630Research output: Contribution to journal > Research article
• Neighborhood Rank Order Coding for Robust Texture Analysis and Feature ExtractionMayr, C. & Schüffny, R., 1 Dec 2007, Proceedings of 7th International Conference on Hybrid Intelligent Systems HIS 2007. p. 290-295, 6 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Abbildung komplexer, pulsierender, neuronaler Netzwerke auf spezielle neuronale VLSI HardwareWendt, K., Ehrlich, M., Mayr, C. & Schüffny, R., 1 Jun 2007, Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS´2007). p. pp. 127-132Research output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Active Pixel Sensor Arrays in 90/65nm CMOS-Technologies with vertically stacked photodiodesHenker, S., Mayr, C., Schlüßler, J., Schüffny, R., Ramacher, U. & Heittmann, A., 1 Jun 2007, In: International Image Sensor Workshop (IISS). p. 16-19, 4 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article
• Modellierung eines Wafer-Scale Systems für pulsgekoppelte neuronale NetzeScholze, S., Ehrlich, M. & Schüffny, R., 1 Jun 2007, Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS´2007). Hardt, W. (ed.). TUDpress/Thelem Universitätsverlag, p. pp. 61-66Research output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• SYMPAD – A Class Library for Processing Parallel Algorithm SpecificationsRullmann, M., Schaffer, R., Siegel, S. & Merker, R., 1 May 2007, Dresdner Arbeitstagung Schaltungs und Systementwurf (DASS). Dresden, Germany, p. 93-98, 6 p.Research output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• A Reconfiguration Aware Circuit Mapper for FPGAsRullmann, M. & Merker, R., 1 Apr 2007, IEEE International Parallel & Distributed Processing Symposium - IPDPS 2007, 14th Reconfigurable Architectures Workshop. Long Beach, USAElectronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable ArchitectureRullmann, M., Siegel, S., Merker, R., Filho, J. A. O., Schweizer, T., Oppold, T. & Rosenstiel, W., 1 Mar 2007, 20th International Conference on Architecture of Computing Systems (ARCS'07) - Workshop on Dynamically Reconfigurable Systems (DRS). Zurich, Switzerland, p. 141-150, 10 p.Research output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Wafer-scale VLSI implementations of pulse coupled neural networksEhrlich, M., Mayr, C., Eisenreich, H., Henker, S., Srowig, A., Grübl, A., Schemmel, J. & 1 others, 1 Mar 2007, 4th Multi-Conference on Systems, Signals & Devices (SSD'07). p. 409, 1 p.Research output: Contribution to book/conference proceedings/anthology/report > Conference contribution

2006

• Design techniques for deep submicron CMOS / Case study Delta-Sigma-ModulatorEllguth, G., Mayr, C., Henker, S. & Schüffny, R., 1 May 2006, Dresdner Arbeitstagung Schaltungs- und Systementwurf 2006. p. 35-40, 6 p.Research output: Contribution to book/conference proceedings/anthology/report > Conference contribution