publications

2012

• Dedicated FPGA Communication Architecture and Design for a Large-Scale Neuromorphic SystemThanasoulis, V., Partzsch, J., Hartmann, S., Mayr, C. & Schüffny, R., 1 Dec 2012, 19th IEEE International Conference on Electronics, Circuits, and Systems. p. 877-880, 4 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Essentials for operating memristive arrays: A BiFeO3 studyPartzsch, J., Mayr, C., Schüffny, R. & Schmidt, H., 1 Dec 2012, MemCo Workshop "Memristors for Computing"Research output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Long-Term Pulse Stimulation and Recording in an Accelerated Neuromorphic SystemThanasoulis, V., Partzsch, J., Vogginger, B., Mayr, C. & Schüffny, R., 1 Dec 2012, 19th IEEE International Conference on Electronics, Circuits, and Systems. p. 590-592, 3 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Waveform Driven Plasticity in BiFeO3 Memristive Devices: Model and ImplementationMayr, C., Stärke, P., Partzsch, J., Cederstroem, L., Schüffny, R., Shuai, Y., Du, N. & 1 others, 1 Dec 2012, Neural Information Processing Systems. p. 1-9, 9 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC LinksHöppner, S., Walter, D., Ellguth, G. & Schüffny, R., 1 Mar 2012, In: International Journal of Embedded and Real-Time Communication Systems (IJERTCS). 3, 4, p. 42-56, 15 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article

2011

• Demo: Waferscale Communication infrastructureMayr, C., Partzsch, J., Scholze, S. & Schüffny, R., 1 Dec 2011, Fet11 - The European Future Technologies Conference and ExhibitionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Design Flow Integration of the Linearized Operating Point (LOP) MethodHöppner, S., Henker, S., Görner, J. & Schüffny, R., 1 Dec 2011, MunEDA User Group MeetingElectronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• IP Porting and Resizing for High-Speed NoC Links from 65nm to 28nm Globalfoundries CMOS Technology with WiCkeDWalter, D., Höppner, S. & Schüffny, R., 1 Dec 2011, MunEDA User Group MeetingElectronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Mismatch Characterization of High-Speed NoC Links using Asynchronous Sub-SamplingHöppner, S., Walter, D., Ellguth, G. & Schüffny, R., 1 Dec 2011, IEEE International Symposium on System on Chip. p. 112-115, 4 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution

2010

• Exploration of Feasible Voltage Ranges in Analog CMOS Circuits Using Linearized-Operating-Point Transistor ModelsHöppner, S., Henker, S., Schüffny, R. & Graupner, A., 1 Dec 2010, MunEDA User Group MeetingElectronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution