publications
publications:
204 Entries
2020
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Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems , 2020, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39, 8, p. 1635-1648Electronic (full-text) versionResearch output: Contribution to journal > Research article
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Plasticity and Adaptation in Neuromorphic Biohybrid Systems , 2020, In: iScience. 23, 10, 101589Electronic (full-text) versionResearch output: Contribution to journal > Review article
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Real-time Hardware Implementation of ARM CoreSight Trace Decoder , 2020, In: IEEE design & test : D & T. 38, 1, p. 69-77, 9 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article
2019
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Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS , Oct 2019, VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings. Metzler, C., De Micheli, G., Gaillardon, P., Silva-Cardenas, C. & Reis, R. (eds.). IEEE Computer Society, p. 155-158, 4 p., 8920295Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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Dynamic Power Management for Neuromorphic Many-Core Systems , Aug 2019, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 8, p. 2973-2986, 14 p., 8701528Electronic (full-text) versionResearch output: Contribution to journal > Research article
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A Biohybrid Setup for Coupling Biological and Neuromorphic Neural Networks , 1 May 2019, In: Frontiers in neuroscience. 13, MAY, 432Electronic (full-text) versionResearch output: Contribution to journal > Research article
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A fast lock-in ultra low-voltage ADPLL clock generator with adaptive body biasing in 22nm FDSOI technology , 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702109Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration , 2019, p. 1-5Electronic (full-text) versionResearch output: Contribution to conferences > Paper
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An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~ W/Channel in 65-nm CMOS , 2019, In: IEEE transactions on very large scale integration (VLSI) systems. 27, 1, p. 126-137, 12 p.Research output: Contribution to journal > Research article
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Design Challenges of Real-time Hardware Implementation of Seizure Prediction Chip , 2019Research output: Contribution to conferences > Paper