Neuromorphic VLSI Systems

(as of 17.03.2025)

Lecturer

Prof. Dr.-Ing. habil. Christian Mayr,

Dr.-Ing. Johannes Partzsch,

Dipl.-Phys. Bernhard Vogginger
   
Contact persons

Dr.-Ing. Johannes Partzsch
Module "Neuromorphic VLSI systems"
"Neuromorphic VLSI-Systems"
EuI-IST-E-NVLSI, EuI-NES-E-NVLSI
module description (previous version: ET-12 08 27) /(previous version: NES-12 08 06)
Scope and type 4 semester hours per week (SWS) Lecture,
2 SWS exercise
Examination Project work and presentation
(according to module description)
Dates/timetable

Summer semester 2025
(timetable)

  • annually in the summer semester

Compulsory elective module for

  • the Electrical Engineering degree program
    (Master and Diploma), fields of study: Information Technology and Microelectronics
  • the degree program Nanoelectronic Systems
    (Master)
  • the Information Systems Engineering degree program in the field of Electronic Circuits and Systems
Teaching material Page with teaching material
Content of the course

The content of the module includes

  • Design methods for integrated analog CMOS circuits and their circuit dimensioning
  • Neuromorphic VLSI systems and their neurobiological foundations, common abstraction models, as well as their use in research and technology, e.g. in brain-machine interfaces and for signal processing
  • Fundamentals, concepts and methods for the creation and analysis of analog and neuromorphic CMOS circuits with the design software Cadence DF2

The module is divided into lectures on the basics of
neuromorphic systems and CMOS circuit design, as well as accompanying computer exercises on the corresponding VLSI design tools.

The module is offered in English.
Qualification goals After completing the module, students will be familiar with the
the field of neural networks from the neurobiological
fundamentals to the application circuit. They will be able to
able to use industrial design tools (Cadence DF2,
Spectre), design CMOS circuits, dimensioning, verifying the performance parameters by parameters by simulation and create the corresponding circuit layouts.

About this page

Jürgen Dohndorf
Last modified: Mar 17, 2025