Publications
218 Entries
2026
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A Near-Cache RISC-V Coprocessor for Efficient Posit Dot-Product Acceleration, 4 Sep 2026, 2026 IEEE 37th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE Canada, p. 159-160, 2 p., 11695626Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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A Configurable RISC-V Co-Processor with Instruction-Controlled Stream-Based Accelerators, Sep 2026, In: ACM transactions on reconfigurable technology and Systems : TRETS. 19, 3, p. 1-32, 32 p., 34Electronic (full-text) versionResearch output: Contribution to journal > Research article
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FDBench: A Paired Golden-Buggy Benchmark for FPGA Debugging, 13 Aug 2026, Proceedings of the 16th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2026. Abdelhamid, R. B., Cheung, R., Hannig, F., Shanker, S., Koch, D., Takamaeda, S. & Stojilovic, M. (eds.). Association for Computing Machinery (ACM), p. 161-163, 3 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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Access control and security analysis of shared accelerators with hardware-level scheduling, Aug 2026, In: Microprocessors and Microsystems. 123, 105186Electronic (full-text) versionResearch output: Contribution to journal > Research article
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MoSim: A Modular Simulation Framework for FPGA-based Systolic CNN Accelerators, 18 Jun 2026, ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers (IEEE), p. 773-777, 5 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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A RISC-V Coprocessor to Accelerate Structured Sparse-Dense Matrix Multiplications, Jun 2026, ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers (IEEE), p. 1601-1605, 5 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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Integrating an open-source soft-GPU overlay with RISC-V control and high-bandwidth memory, Jun 2026, In: Journal of Systems Architecture. 175, 103736Electronic (full-text) versionResearch output: Contribution to journal > Research article
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ProCon-V: A Programmable Tightly Coupled Convolution Accelerator Based on RISC-V Custom Instructions for Edge Devices, May 2026, In: IEEE transactions on computers. 75, 5, p. 1991-2006, 16 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article
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Towards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge Applications, Mar 2026, Proceedings - 35th International Conference on Field-Programmable Logic and Applications, FPL 2025. Institute of Electrical and Electronics Engineers (IEEE), p. 273-281, 9 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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6G network design and operations, 13 Feb 2026, 6G-life: Unveiling the Future of Technological Sovereignty, Sustainability, and Trustworthiness. Elsevier, p. 135-149, 15 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Chapter in book/Anthology/Report