Publications

2017

• HW/SW Co-Design of the HOG algorithm on a Xilinx Zynq SoCRettkowski, J., Boutros, A. & Göhringer, D., Nov 2017, In: Journal of parallel and distributed computing. 109, p. 50-62, 13 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article
• Data Stream Processing in Networks-on-ChipRettkowski, J. & Göhringer, D., 20 Jul 2017, 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. Reis, R., Stan, M., Huebner, M. & Voros, N. (eds.). IEEE Computer Society, p. 633-638, 6 p., 7987593Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Access Network Generation for Efficient Debugging of FPGAsKhan, H. U. H., Grimm, T., Hübner, M. & Göhringer, D., 7 Jun 2017, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. 6 p., 25Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• A call-up for circuit-switched NoCs in the Dark-Silicon EraHesham, S., Göhringer, D. & Ghany, M. A. E., 2017, p. 1-6, 6 p.Electronic (full-text) versionResearch output: Contribution to conferences > Paper
• Accelerated Embedded AKAZE Feature Detection Algorithm on FPGAKalms, L., Mohamed, K. & Göhringer, D., 2017, p. 1–6Electronic (full-text) versionResearch output: Contribution to conferences > Paper
• An event-based Network-on-Chip debugging system for FPGA-based MPSoCsKhan, H. U. H., Rettkowski, J., Eldafrawy, M. & Göhringer, D., 2017, p. 30-37, 8 p.Research output: Contribution to conferences > Paper
• Application-specific processing using high-level synthesis for networks-on-chipRettkowski, J. & Göhringer, D., 2017, p. 1-7, 7 p.Electronic (full-text) versionResearch output: Contribution to conferences > Paper
• Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUsKalms, L. & Göhringer, D., 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL). IEEE Xplore, 4 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• HW/SW Co-design of an IEEE 802.11a/G Receiver on Xilinx Zynq SoC Using High-Level SynthesisNouri, S., Rettkowski, J., Göhringer, D. & Nurmi, J., 2017, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. 6 p., 15Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
• Robust lane recognition for autonomous drivingKalms, L., Rettkowski, J., Hamme, M. & Göhringer, D., 2017, p. 1-6, 6 p.Electronic (full-text) versionResearch output: Contribution to conferences > Paper