2017
ZABEl, M.; BRINKER, M.; KÖHLER, S.; SPALLEK, R.G.:
Failure-Rate Analysis based on Microprocessor Trace Data.
In: Proceedings of Reliability by Design; 9. ITG/GMM/GI-Symposium, Hamburg, Sep.2017
ISBN: 978-3-8007-4444-2
http://ieeexplore.ieee.org/document/8084537/?reload=true
KNODEL, O.; GENßLER, P. ; SPALLEK, R. G.:
Virtualizing Reconfigurable Hardware to Provide Scalability in Cloud Architectures.
In: The Tenth International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS), Rome, Sep, 2017
KNODEL, O.; KÖHLER, S.; RÖßLER, M.; SPALLEK, R.G.:
First Workshop on Hardware Defined Programming - HDP
In: INFORMATIK 2017. Lecture Notes in Informatics (LNI), Volume P, GI Bonn 2017,
S 275
ISBN 978-3-88579-669-5
GENßLER, P.; KNODEL, O.; SPALLEK, R.G.:
A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture.
In: INFORMATIK 2017. Lecture Notes in Informatics (LNI), Volume P, GI Bonn 2017.
S 531--542
ISBN 978-3-88579-669-5
https://dl.gi.de/handle/20.500.12116/4067
RUSSELL, P;; DÖGE, J.; HOPPE, C.; PREUßER, T.; REICHEL, P.; SCHNEIDER,P.: Implementation of an Asynchronous Bundled-Data Router for a GALS NoC in the Context of a VSoC, 20th International IEEE Symposium on Design and Diagnostics of Electronic Circuits Systems.
In: DDECS 2017, Dresden, Apr, 2017.
S. 195--200.
DOI: 10.1109/DDECS.2017.7934579
http://ieeexplore.ieee.org/document/7934579
PREUßER, T.:
In: Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs.
In: International Conference on Field Programmable Logic and Applications (FPL 2017), Ghent, Sep, 2017.
DOI 10.23919/FPL.2017.8056834
http://ieeexplore.ieee.org/document/8056834/
PREUßER, T; BLOTT, M.; FRASER, N.; GAMBARDELLA, G.; O'BRIEN, K.; VISSERS, K.; UMUROGLU, Y.:
Keynote: Quantized Neural Networks on All Programmable Devices, 1st FPL Workshop on Reconfigurable Computing for Deep Learning.
In: RC4DL 2017, Ghent, Sep, 2017.
http://www.ece.ucy.ac.cy/labs/easoc/RC4DL/keynotes.html
BLOTT, M.; PREUßER, T.; FRASER, N.; GAMBARDELLA, G.; O'BRIEN, K.; Umuroglu, Y.; LEESER, M.:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic.
In: International IEEE Conference on Computer Design (ICCD 2017),Boston, Nov, 2017.
S. 419--422,
DOI 10.1109/ICCD.2017.73,
http://ieeexplore.ieee.org/document/8119246
KÖHLER, S.; SPALLEK, R.G.:
Custom Hardware Integration into DBT-based Processor Simulation.
In: The Tenth International Conference on Advances in Circuits,
Electronics and Micro-electronics, CENICS 2017, Rome, September, 2017.
ISBN: 978-1-61208-585-2
KÖHLER, S.; SPALLEK, R.G.:
Modellierung anwendungsspezifischer Hardware und deren Einbettung in die
DBT-basierte Prozessor-Verhaltenssimulation.
In: 47. Jahrestagung der Gesellschaft für Informatik, Informatik, Chemnitz, 2017.
ISBN 978-3-88579-669-5