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SpiNNaker2 Hardware Platform

SpiNNaker2 Overview

A brief description of the SpiNNaker2 chip and architecture will follow.

For a first overview, see [Hoeppner and Mayr 2018] or [Mayr et al. 2018].

Comparison of SpiNNaker2 platforms and SpiNNaker 1

Details about MAC accelerator

SpiNNaker2 and its prototype chips contain a dedicated machine learning accelerator into each processing element:

• 64 Multiply-Accumulate (MAC) units with 8 bit multiplier and 29 bit accumulator running 64 MAC operations per clock cycle
• two operation modes:
  • 2D convolution (highly configurable)
  • matrix multiplication
• signed/unsigned integer
• 4 MAC units each can be combined to form a 16-bit MAC unit for higher precision, at the cost of reducing the paralle execution to 16 instead of 64
• Rectified Linear Unit (ReLU) and built-in quantization at no extra cost
• Can be used for inference of deep neural networks, signal processing or speed up of spiking neural networks
• Two ways to start MAC accelerator:
  • C function call from ARM programm. ARM processor can run different code while MAC acc. operates.
  • via NoC packets, e.g., from remote processing element. MAC acclerator can run without ARM processsor enabled

More details can be found in [Kelber and Wu et al. 2020]  and [Yan et al. 2020]

Fixed-point Exp/Log function accelerator

Each SpiNNaker2 processing element contains a hardware accelerator for the exponential and natural logarithm functions in the fixed point format.

• Throughput: 20.8M-50M exp/s
• Latency: 5-12 cycles
• accuracy control to trade-off between accuracy and latency
• Much faster than equivalent software implementation on ARM core (95 cycles) and no usage of SRAM ressources needed for Look-up tables

For more details, see [Mikaitis et al. 2018]

Random number generators

More information of Pseudo RNG can be found in [Yan et al. 2019]

How will the SpiNNaker2 User Interface look like?

In the long term there will be the following high-level interfaces to SpiNNaker2:

• PyNN interface for spiking neural networks. This is based on spyNNaker implementation of SpiNNaker1. The software porting is already ongoing
• TensorFlow-like interface for deep neural network inference. Other frameworks can be supported via ONNX.
• Hybrid spiking and deep network will be also supported

Currently available (October 2020):

• Chip-side: Low-level C-library  for ARM code for support of all SpiNNaker2 processing element-specific functions,  e.g., accelerators, direct memory access (DMA) etc.
• Host-side: C++ software for simple setup, configuration and control of Jib-1 or FPGA prototype
• Examples: Many examples for usage of all accelerators, SNN simulation on multiple PEs

Planned for spring 2021:

• Release of 1st high-level interface for spiking networks and deep networks. Will be based on spyNNaker from SpiNNaker 1. Platform: SpiNNaker2 FPGA Prototype

Questions regarding SpiNNaker2 Award

Which kind of proposals will be considered?

For example application areas, please see the Call.

All projects should evaluate or highlight the potential of SpiNNaker2. Obviously, within the provided funding only  smaller pilot studies are possible that can build the foundation of future larger joint project undertakings.

Example projects could contain, but are not limited to:

• Novel SNN/DNN architectures or learning mechanisms, that make use of new accelerators in SpiNNaker2 or have a high scientific potential.  C-implementation on ARM cores. For example:
  • hybrid SNN / DNN approaches
  • novel spiking or non-spiking learning mechanisms

• Efficient SNN processing: E.g, porting of existing small-scale SpiNNaker1 applications that greatly benefit from new features in SpiNNaker2 like hardware accelerators (MAC, exp/log, RNG) or floating point support
• Sensor, Robotic or Bio-signal processing, that make use of new SpiNNaker2 features
• Mixed low-level & scaling studies: The SpiNNaker system stands out by its scalability for highly-parallel real-time processing with event-based communication. However, for the first SpiNNaker2-Award projects, only small-scale hardware systems will be available (see question below), so that these key aspects of SpiNNaker2 can not play off. Still, scalability could be considered e.g. by a node-level implementation of code and an accompanying scalability study (pen-and-paper, Excel,system simulation).
• Multi-scale brain simulation: e.g. projects that contain both simulation of spiking neurons and their interaction with coarser models of populations or brain areas. Efficient C-implementation for both, possibly using accelerators.

Which hardware platform will be available for the SpiNNaker2 Award?

There are two platforms available in the first round of the SpiNNaker2 Award in 2021:

• Jib1 SpiNNaker2 Prototype Platform, see above and [Yan et al. 2020]
  • Contains 8 ARM cores, a SpiNNaker router
  • Up to 4 Chips on 1 PCB
  • no DRAM
  • first version of MAC accelerator (8-bit unsigned integer operation, no ReLU)
  • Configuration and control via JTAG (Host software available)
  • Interfacing sensors etc. via GPIO, e.g. UART, SPI
• SpiNNaker2 FPGA prototype
  • Synthesized on Xilinx Virtex Ultrascale+ VCU118
  • 16 ARM M4F on 4 QuadPEs identical to those in final SpiNNaker2, latest MAC accelerator
  • 65 MHz clock frequency
  • no SpiNNaker router
  • 64 MBit SRAM as surrogate for missing DRAM
  • 1-Gbit Ethernet access via UDP
  • high-level software interface to be released in spring 2021

Access to SpiNNaker2 Hardware? Will I get a board and chip for the Award?

For the awarded projects in the first year, two hardware systems (Jib-1 test chip or SpiNNaker2 FPGA prototype) will be available, see also this question.

• For projects that want to connect the SpiNNaker2 prototype to sensor or actuators, a Jib-1 board could be borrowed with remote support.
• For other projects the SpiNNaker2 FPGA prototype is recommended, as it is consistent with the latest state of chip design and has the best software support. Remote access is recommended. Awardees could also use the money to buy their own setup.
• Remote access to Jib-1 or FPGA prototype for algorithm development and characterization is possible for all projects
• In any case, continuous software support will be provided by members of the TU Dresden HPSN chair

Publications and presentations related to SpiNNaker2

• Y. Yan et al., "Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi." https://arxiv.org/abs/2009.08921
• C. Mayr et al., “SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning.”  https://arxiv.org/abs/1911.02385
• F. Kelber, B. Wu, B. Vogginger, J. Partzsch, C. Liu, M. Stolba and C. Mayr. Mapping Deep Neural Networks on SpiNNaker2. In NICE 2020: Neuro-Inspired Computational Elements Workshop, 2020.
• M. Mikaitis et al. "Approximate fixed-point elementary function accelerator for the SpiNNaker-2 Neuromorphic Chip." 2018 IEEE 25th Symposium on Computer Arithmetic (ARITH). IEEE, 2018. https://ieeexplore.ieee.org/abstract/document/8464785
• Y. Yan et al., "Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype," in IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 3, pp. 579-591, June 2019, doi: 10.1109/TBCAS.2019.2906401.
• S. Furber et al. "Overview of the spinnaker system architecture." IEEE Transactions on Computers 62.12 (2012): 2454-2467. https://ieeexplore.ieee.org/abstract/document/6226357
• S. Höppner and C. Mayr. "Spinnaker2-towards extremely efficient digital neuromorphics and multi-scale brain emulation." Proc. NICE. 2018. Video Slides