Comparing Multi-Bit EDAC in Hardware and Software

Error correction code (ECC) DRAM typically allows for one-bit error correction and two-bit error detection. However, this type of memory is usually more expensive and consumes more power than conventional DRAM. More advanced multi-bit error correction and detection capabilities compound these drawbacks additionally.
The aim of this master's thesis will be to analyse the potential of targeted software-implemented fault tolerance methods by comparing them to common ECC DRAM, using a simulation for virtual fault injection that considers a multi-bit error focused fault mode.

(Master Thesis status talk)