Abeer Khan: FPGA-optimized implementation of an Arithmetic Logic Unit (ALU) for a RISC-V processor (Intermediate presentation project work)

16.05.2023, 10:00 am

Invitation to the intermediate presentation of Mr. Abeer Khan

Topic: FPGA-optimized implementation of an Arithmetic Logic Unit (ALU) for a RISC-V processor

Project: Project work

Supervisors: Muhammad Ali, Markus Helbig