Matthias Von Ameln: A Hardware/Software Co-design for a Co-processor evaluation for RISC-V (Diploma thesis)

15.10.2020, 11.00 am

Invitation to the presentation of Mr. Matthias Von Ameln

Topic: A Hardware/Software Co-design for a Co-processor evaluation for RISC-V

Project: Diplomarbeit

Supervisor: Muhammad Ali

Abstract: This work investigates the co-processor integration with a RISC-V core and its evaluation with different SoC topologies. For high performance computing, different SoC architectures are used e.g. hardware accelerators, GPPs, ASICs, etc. There are different hardware topologies to adapt hardware accelerators with general purpose processors. This allows control from software side of the processor and adds flexibility in using accelerators of the system. In this work, an already available RISC-V based processor (RI5CY) will be used for research work. RISC-V is an open source instruction set architecture developed by the University of California, Berkeley. RISC-V also has a free available toolchain. RISC-V allows developers to add custom instructions to its ISA which helps maintain the backward and forward compatibility of the ISA. This characteristic of RISC-V can be used to add instructions that are application specific to improve performance and accuracy. For this work a custom interface needs to be implemented for communication between RISC-V processor (core and data memory) and co-processor. For controlling the coprocessor functionality custom instructions needs to be added to the processor and the RISC-V toolchain. Co-processor design should be vector based (using integer data type) on a function e.g. matrix multiplication, convolution or an image processing filter. This would be used in evaluation when comparing single RISC-V with RISC-V with co-processor and RISC-V cluster. A boarder line should be defined to when it is more feasible to add co-processor to the system and when a cluster will be more feasible. Finally, the student needs to document his implementation and findings.