Satya Swapna Kommisetti: FPGA-optimized Hardware Accelerator for Matrix Multiplication based on Systolic Arrays (Intermediate presentation project work)

26.10.2022, 14:00 pm

Invitation to the intermediate presentation of Satya Swapna Kommisetti

Topic: FPGA-optimized Hardware Accelerator for Matrix Multiplication based on Systolic Arrays

Project: Project work

Supervisors: Ahmed Kamal, Markus Helbig