Saul Isaac Sanchez Flores: Hardware Task Scheduler with Access Control (Project work)

25.06.2024, 14:00 pm, APB 1096

Invitation to the presentation of Mr. Saul Isaac Sanchez Flores

Topic: Hardware Task Scheduler with Access Control

Project: Project work

Supervisor: Cornelia Wulf

Abstract: Secure and efficient hardware acceleration is crucial for modern applications, especially in virtualized environments where multiple applications share resources on a Field-Programmable Gate Array (FPGA). This work explores a novel approach that takes advantage of the features that High-Level Synthesis (HLS) has to offer to address this challenge. The report details the development of an IP core for scheduling hardware tasks on a Xilinx Zynq Ultra FPGA. This core, designed using Vivado HLS, is targeted to be called by software tasks to access different available acceleration modules. The system utilizes the AXI4 Lite interface for memory-mapped communication, ensuring secure access control to hardware accelerators as facilitated by access control mechanisms such as the L4Re micro-kernel. This combined approach promotes efficient hardware utilization while maintaining system security in virtualized reconfigurable systems.