Sisi Wu: Development of a cache-coherent system for RISC-V based MPSoC (Intermediate presentation master thesis)

05.10.2023, 13:00 pm

Invitation to the intermediate presentation of Ms. Sisi Wu  

Topic: Development of a cache-coherent system for RISC-V based MPSoC

Project: NES master thesis 

Supervisors: Ahmed Kamal, Matthias Nickel