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Sep 16, 2020
Tim Häring: Computer Vision Algorithm Design using High-Level Synthesis (Profilprojekt Anwendungsforschung in der Informatik)
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Tim Häring: Computer Vision Algorithm Design using High-Level Synthesis (Profilprojekt Anwendungsforschung in der Informatik)
Sep 11, 2020
Tianmu Cheng: Design of a Model Predictive Controller for a Mobile FPGA-Based Robotic Platform (Projektarbeit)
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Tianmu Cheng: Design of a Model Predictive Controller for a Mobile FPGA-Based Robotic Platform (Projektarbeit)
Sep 11, 2020
Bozhidar Kolarov: Development of various routing algorithms for extending a NoC simulator (Studienarbeit)
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Bozhidar Kolarov: Development of various routing algorithms for extending a NoC simulator (Studienarbeit)
Aug 26, 2020
Muhammad Zaid: A Hardware/Software Co-design for machine learning (intermediate presentation project work)
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Muhammad Zaid: A Hardware/Software Co-design for machine learning (intermediate presentation project work)
Aug 21, 2020
Sebastian Reimers: Management of HW-accelerators in L4Re (Forschungsprojekt Anwendung)
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Sebastian Reimers: Management of HW-accelerators in L4Re (Forschungsprojekt Anwendung)
Aug 17, 2020
Welcome, Sergio Pertuz!
The chair of Adaptive Dynamic Systems welcomes our new member of staff Sergio Andres Pertuz .
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Welcome, Sergio Pertuz!
Aug 11, 2020
Tim Häring: Computer Vision Algorithm Design using High-Level Synthesis (intermediate presentation Profilprojekt Anwendungsforschung in der Informatik)
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Tim Häring: Computer Vision Algorithm Design using High-Level Synthesis (intermediate presentation Profilprojekt Anwendungsforschung in der Informatik)
Jul 31, 2020
Lester Kalms: Methods and Algorithms for an Efficient Programming of FPGA-based Heterogeneous Systems for Object Detection (Statusvortrag)
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Lester Kalms: Methods and Algorithms for an Efficient Programming of FPGA-based Heterogeneous Systems for Object Detection (Statusvortrag)
Jul 15, 2020
Karl Friebel: Sycl zu C99 basierter Transpiler zur Generierung von datenflussorientierten FPGA-Beschleunigern (intermediate presentation Diplomarbeit)
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Karl Friebel: Sycl zu C99 basierter Transpiler zur Generierung von datenflussorientierten FPGA-Beschleunigern (intermediate presentation Diplomarbeit)
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