Topics for Student Theses
Table of contents
All topics in this list are available for Bachelor, Undergraduate, Diploma, and Master theses. We will discuss with you to scale the topic appropriately. Your own topic proposals are also very welcome.
High-performance Architectures
Systems in high-performance computing (HPC) need to cater to the demanding nature of applications in this field. Traditional requirements include low latency networking, cache-optimal memory placement, and timely coordination between compute nodes in the system. More recently, energy considerations have also become a concern. We study the implications these requirements and the specialised HPC hardware have for system-level software.
Scheduling
The scheduling of processes or threads in different environments (e.g. realtime, distributed, or high-performance systems) is governed by a diverse set of optimisation goals: throughput, timeliness, energy conservation, quality-of-service guarantees, to name but a few. Our work in this area tries to incorporate new approaches like machine learning or explores new areas like disaggregated systems.
System Architecture
Trusted Computing
Trusted Execution Environments (TEEs) enable secure execution of programs, including protections from an operating system or hypervisor that got compromised. TEEs typically integrate with remote attestation in order to securely report identity and integrity of the program in the TEE (and the TEE itself) to a remote party. The combination of TEEs, remote attestation, and microkernel-based system architectures such as L4 and M3 present opportunities to build more trustworthy systems. Get in touch to discuss possible topics.
Supervisor: Carsten Weinhold
Virtualization
Fault Tolerance and Fault Injection
Computers are usually assumed to always work correctly and predictably, as defined in the program code. While this is generally correct, there may be internal and external influences that effect this assumption. Internal influences can be undetected production errors, which become more likely as the structure size of the chips becomes increasingly smaller. While external influences can be radiation particles, which pass through the chips and lead for example to ionization in the transistors. Especially if these errors occur only very rarely and the system architecture is based on the assumption that exactly what is defined in the code will happen, severe consequences can be the result.
To counter this, we study the possibilities of software-implemented hardware fault tolerance (SIHFT), in which faults are detected with the help of software. This variant can also be integrated after the hardware is developed and produced and is therefore also applicable for commercial off-the-shelf hardware. Since redundant hardware is expensive to develop, SIHFT has many possible areas to be applied, for example in cubesats or cars.
In particular, we evaluate SIHFT methods with the fault-injection framework FAIL*, which can imitate hardware faults caused by radiation effects and systematically examine a program regarding its fault tolerance.
Miscellaneous
This category comprises topics that don't fit any of the other categories.
Ohua is a source-to-source compiler that is developed at Barkhausen Institute to simplify isolation of multiple components that are part of a single application. Ohua takes monolithic code as input and generates componentized code that can use different isolation mechanisms. So far, we have implemented compiler backends for MMU-based isolation as it is used by code running in separate address spaces.
Intel MPK (Memory Protection Keys) however is a more lightweight isolation mechanism: It works by quickly enabling and disabling access to different parts of the same virtual address space. Other works like FlexOS or CubicleOS already use this isolation mechanism.
The goal of this thesis is to package Intel MPK so that it is digestible by Ohua as an isolation backend. This entails the implementation of compartment setup within an address space using MPK as well as communication primitives between these compartments. A performance and security comparison with MMU-based isolation can show the relative advantages and disadvantages of these isolation mechanisms.
Advisor: Michael Roitzsch