Dr.-Ing. Ahmed Kamaledin Atef
© Ahmed Kamal
Postdoc
NameMr Dr.-Ing. Ahmed Kamaledin Atef
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Visiting address:
Andreas-Pfitzmann-Bau (APB), 1099 Nöthnitzer Str. 46
01187 Dresden
Short CV:
Ahmed Kamaledin Atef is a postdoc in the Chair of Adaptive Dynamic Systems (ADS) at Fakultät Informatik TU-Dresden, Deutschland, since July 2023. He was a PhD candidate and a research fellow since September 2017. Before joining the ADS research group, he received his M.Sc degree in Electronics and Electrical communications from Cairo University, Egypt in 2017 and his B.Sc in Electronics and Electrical communications from Cairo University, Egypt in 2012 (with honor degree).Google Scholar Linkedin
Research Interests:
His current research interests are in the hardware implementation of real-time heterogeneous reconfigurable systems for edge applications.
Publications:
2026
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MoSim: A Modular Simulation Framework for FPGA-based Systolic CNN Accelerators, 18 Jun 2026, ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers (IEEE), p. 773-777, 5 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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A RISC-V Coprocessor to Accelerate Structured Sparse-Dense Matrix Multiplications, Jun 2026, ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers (IEEE), p. 1601-1605, 5 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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A Configurable RISC-V Co-Processor with Instruction-Controlled Stream-Based Accelerators, 27 May 2026, In: ACM transactions on reconfigurable technology and Systems : TRETSElectronic (full-text) versionResearch output: Contribution to journal > Research article
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ProCon-V: A Programmable Tightly Coupled Convolution Accelerator Based on RISC-V Custom Instructions for Edge Devices, May 2026, In: IEEE transactions on computers. 75, 5, p. 1991-2006, 16 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article
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Towards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge Applications, Mar 2026, Proceedings - 35th International Conference on Field-Programmable Logic and Applications, FPL 2025. Institute of Electrical and Electronics Engineers (IEEE), p. 273-281, 9 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
2025
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Towards an Energy-Efficient RISC-V Core Architecture with Dynamic Dual-Issue and Clock Gating, Sep 2025, 2025 28th Euromicro Conference on Digital System Design (DSD). Casini, D. & Cazorla, F. J. (eds.).p. 300-307, 8 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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Quantized Semantic Segmentation for Efficient Spectrum Sensing on FPGAs, Jul 2025, 2025 14th International Conference on Modern Circuits and Systems Technologies, MOCAST 2025 - Proceedings. 2025 ed., Institute of Electrical and Electronics Engineers (IEEE)Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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A RISC-V Coprocessor for Seamless Integration of Stream-Based Accelerators, 7 Jun 2025, 2025 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). p. 1221-1227, 7 p., 11106148Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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Towards Computing a Real-Time THz Material Map, 24 Feb 2025, 2025 International Conference on Mobile and Miniaturized Terahertz Systems (ICMMTS). p. 229-231, 3 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
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Exploring RISC-V Instruction-Level Optimization Through Macro-Operation Fusion for TensorFlow-based Models, 2025, 2025 IEEE 38th International System-on-Chip Conference (SOCC). Zhao, D. & Hofmann, K. (eds.).p. 1-6, 6 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution