Dr.-Ing. Ahmed Kamaledin Atef
© Ahmed Kamal
Postdoktorand
NameHerr Dr.-Ing. Ahmed Kamaledin Atef
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Besuchsadresse:
Andreas-Pfitzmann-Bau (APB), 1099 Nöthnitzer Str. 46
01187 Dresden
Short CV:
Ahmed Kamaledin Atef is a postdoc in the Chair of Adaptive Dynamic Systems (ADS) at Fakultät Informatik TU-Dresden, Deutschland, since July 2023. He was a PhD candidate and a research fellow since September 2017. Before joining the ADS research group, he received his M.Sc degree in Electronics and Electrical communications from Cairo University, Egypt in 2017 and his B.Sc in Electronics and Electrical communications from Cairo University, Egypt in 2012 (with honor degree).Google Scholar Linkedin
Research Interests:
His current research interests are in the hardware implementation of real-time heterogeneous reconfigurable systems for edge applications.
Publications:
2023
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Acceleration of 2D SAR Imaging on FPGA by Reducing off-chip Memory Accesses, 3 Juli 2023, 2023 6th International Workshop on Mobile Terahertz Systems, IWMTS 2023. Institute of Electrical and Electronics Engineers Inc., S. 1-5Elektronische (Volltext-)VersionPublikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Konferenzband
2022
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Hardware/Software Co-design of 2D THz SAR Imaging for FPGA-based Systems-on-Chip, 21 Juli 2022, S. 1-5, 5 S.Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
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AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors, 18 April 2022, in: IEEE Access. 10, S. 43895-43913, 19 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Fachzeitschrift > Forschungsartikel
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A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems, 2022, 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL). IEEE Xplore, S. 300-306, 7 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Konferenzband
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An Agile Tile-based Platform for Adaptive Heterogeneous Many-Core Systems, 2022, S. 1-4Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
2021
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FPGA-Based Acceleration of THz SAR Imaging, 5 Juli 2021, S. 1-6, 6 S.Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
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Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures, 2021, Proceedings - 2021 31st International Conference on Field-Programmable Logic and Applications, FPL 2021. IEEE Xplore, S. 265-266, 2 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Konferenzband
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RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip, 2021, 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW): Portland, OR, USA. S. 172-179, 8 S., 9460688Elektronische (Volltext-)VersionPublikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Konferenzband
2020
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Hardware/Software Co-design for the Signal Processing of Dielectric Materials Characterization, 2020, S. 1-6, 6 S.Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
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Towards a Modular RISC-V based Many-Core Architecture for FPGA Accelerators, 2020, in: IEEE Access. S. 1-15, 15 S.Publikation: Beitrag in Fachzeitschrift > Forschungsartikel
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