Dr.-Ing. Ariel Podlubne
© Ariel Podlubne
Postdoktorand
NameDr.-Ing. Ariel Podlubne
Eine verschlüsselte E-Mail über das SecureMail-Portal versenden (nur für TUD-externe Personen).
Besuchsadresse:
Andreas-Pfitzmann-Bau (APB), 1031 Nöthnitzer Str. 46
01187 Dresden
Short CV:
Ariel Podlubne graduated as an MSc. Electrical Engineer in December 2012 from the National Technological University in Cordóba, Argentina. He specialized in Digital Electronics and Embedded Systems during his studies. He received the “Binid” scholarship in 2013, which is for freshly graduates to start a research career. His workplace was CINTRA UA-CONICET where he designed and developed an FPGA-based tool to optimize heterogeneous data acquisition and processing, in order to conduct tests on human echolocation. He worked for two years at LAAS/CNRS in Toulouse France from june 2014 for the european project Two!Ears developing the robotics testbed used for experiment. He was a PhD Candidate since September 2017 at the Chair of Adaptive Dynamic Systems from TU Dresden and is a postdoc since July 2023.
Research Interests:
His research interests are FPGA-Based architectures for signal and image processing and robotics.
Publications:
2021
-
Model-based Approach for Automatic Generation of Hardware Architectures for Robotics, 2021, in: IEEE Access. 9, S. 140921-140937, 17 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Fachzeitschrift > Forschungsartikel
2020
-
Immersives verteiltes Robotic Co-working: Der Festakt zum Informatik-Jubiläum 2019 mit Mixed-Reality-Fallstudie, Dez. 2020, in: Informatik-Spektrum. 43, 6, S. 425-435, 11 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Fachzeitschrift > Forschungsartikel
-
Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks, 2020, S. 73-83, 11 S.Publikation: Beitrag zu Konferenzen > Paper
2019
-
Cycle-accurate Debugging of Multi-clock Reconfigurable Systems, 2019, S. 1-5Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
-
FPGA-ROS: Methodology to Augment the Robot Operating System with FPGA Designs, 2019, S. 1-5Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
-
HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing, 2019, S. 149-164, 16 S.Publikation: Beitrag zu Konferenzen > Paper
-
Intrusive FPGA-in-the-loop debugging using a rule-based inference system, 2019, in: Microprocessors and Microsystems. S. 185-194, 10 S.Publikation: Beitrag in Fachzeitschrift > Forschungsartikel
2018
-
Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration, 2018, S. 64-69, 6 S.Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
-
Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview., 2018, S. 737-749, 13 S.Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
Diese Informationen werden durch das FIS bereitgestellt.