Dr.-Ing. Ariel Podlubne
© Ariel Podlubne
Postdoc
NameDr.-Ing. Ariel Podlubne
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Visiting address:
Andreas-Pfitzmann-Bau (APB), 1031 Nöthnitzer Str. 46
01187 Dresden
Short CV:
Ariel Podlubne graduated as an MSc. Electrical Engineer in December 2012 from the National Technological University in Cordóba, Argentina. He specialized in Digital Electronics and Embedded Systems during his studies. He received the “Binid” scholarship in 2013, which is for freshly graduates to start a research career. His workplace was CINTRA UA-CONICET where he designed and developed an FPGA-based tool to optimize heterogeneous data acquisition and processing, in order to conduct tests on human echolocation. He worked for two years at LAAS/CNRS in Toulouse France from june 2014 for the european project Two!Ears developing the robotics testbed used for experiment. He was a PhD Candidate since September 2017 at the Chair of Adaptive Dynamic Systems from TU Dresden and is a postdoc since July 2023.
Research Interests:
His research interests are FPGA-Based architectures for signal and image processing and robotics.
Publications:
2021
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Model-based Approach for Automatic Generation of Hardware Architectures for Robotics, 2021, In: IEEE Access. 9, p. 140921-140937, 17 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article
2020
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Immersives verteiltes Robotic Co-working: Der Festakt zum Informatik-Jubiläum 2019 mit Mixed-Reality-Fallstudie, Dec 2020, In: Informatik-Spektrum. 43, 6, p. 425-435, 11 p.Electronic (full-text) versionResearch output: Contribution to journal > Research article
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Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks, 2020, p. 73-83, 11 p.Research output: Contribution to conferences > Paper
2019
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Cycle-accurate Debugging of Multi-clock Reconfigurable Systems, 2019, p. 1-5Electronic (full-text) versionResearch output: Contribution to conferences > Paper
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FPGA-ROS: Methodology to Augment the Robot Operating System with FPGA Designs, 2019, p. 1-5Electronic (full-text) versionResearch output: Contribution to conferences > Paper
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HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing, 2019, p. 149-164, 16 p.Research output: Contribution to conferences > Paper
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Intrusive FPGA-in-the-loop debugging using a rule-based inference system, 2019, In: Microprocessors and Microsystems. p. 185-194, 10 p.Research output: Contribution to journal > Research article
2018
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Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration, 2018, p. 64-69, 6 p.Electronic (full-text) versionResearch output: Contribution to conferences > Paper
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Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview., 2018, p. 737-749, 13 p.Electronic (full-text) versionResearch output: Contribution to conferences > Paper
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