Dipl.-Ing. Julian Haase

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Mr Dipl.-Ing. Julian Haase

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Visiting address:

Andreas-Pfitzmann-Bau (APB), 1039 Nöthnitzer Str. 46

01187 Dresden

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Short CV:

Julian Haase is a PhD student and assistant researcher in Computer Science in the Adaptive Dynamic Systems (ADS) chair at Technische Universität Dresden, Germany, since March 2018. Before joining the chair, he studied Information Systems Engineering at the Technical University in Dresden where he successfully completed his studies as an engineer and received his diploma in 2017.

Research Interests:

His current research interests include network on chip (NoC) and routing
algorithms, as well as reconfigurable computing systems and
multiprocessor systems on chip (MPSoCs).

Publications:

15 Entries

2022

PANACA: An open-source configurable network-on-chip simulation platformHaase, J., Groß, A., Feichter, M. & Göhringer, D., 26 Aug 2022, 2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). p. 1-6, 6 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
Secure communication protocol for network-on-chip with authenticated encryption and recovery mechanismHaase, J., Jaster, S., Franz, E. & Göhringer, D., 14 Jul 2022, 2022 IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP). Pericas, M., Pnevmatikatos, D. N., Trancoso, P. P. M. & Sourdis, I. (eds.).p. 156-160, 5 p.Electronic (full-text) versionResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution

2021

Performance Analysis of Application-Specific Instruction-Set Routers in Networks-on-ChipRettkowski, J., Haase, J., Primus, S., Hübner, M. & Göhringer, D., 2021Research output: Contribution to conferences > Paper

2018

Collector-Emitter voltage based one-step commutation for direct three-level matrix converterLeubner, M., Remus, N. & Haase, J., 2018, 20th European Conference on Power Electronics and Applications, EPE 2018, ECCE Europe: 17-21 September 2018, Riga, Latvia. p. 10-xResearch output: Contribution to book/conference proceedings/anthology/report > Conference contribution
Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial ReconfigurationPodlubne, A., Haase, J., Kalms, L., Akgün, G., Ali, M., Khan, H. U. H., Kamal, A. & 1 others, 2018, p. 64-69, 6 p.Electronic (full-text) versionResearch output: Contribution to conferences > Paper