Cristiana Trifu: Low Power Techniques for Computer Architecture (intermediate presentation Master thesis)

03.07.2020, 14.00 pm

Invitation to the intermediate presentation of Mrs. Cristiana Trifu

Topic: Low Power Techniques for Computer Architecture

Project: Master thesis

Supervisor: Muhammad Ali

Abstract: Computer architecture has made incredible progress over the years. This improvement is from both the technology used to build processors and innovations in processor design. Low power techniques in computer architecture are key components to save energy of the overall system. Since performance optimizations in the computer architecture add up more modules, which increases the area and power consumption of the system. Low power techniques can help reduce power consumption while maintaining the performance requirements of the application. Different techniques can be used to achieve low power requirements e.g. clock gating, dynamic frequency scaling, low power functional units, etc. In this work, the student will work on an already available RISC-V core. RISC-V is an open-source instruction set architecture developed by the University of California, Berkeley (UCB). RISC-V supports 32-bit and 64-bit architectures, with a promise to support 128-bit architectures in the future. In this work, the student will investigate the different state of the art low power techniques that are used for computer architecture design. A comparison is required between state of art low power techniques and the low power techniques implemented in an already available RISC-V based processor. Then a low power technique is to be implemented for an already available RISC-V based processor e.g. clock gating for special functional units, dynamic frequency scaling with a clocking wizard, low power ALU design, etc. The implemented design needs to be verified and evaluated. Evaluation of the implemented design should be performed based on execution delay, area, and power consumption.