Thuemmler: Development of a processor pipeline based on RISC-V ISA

05.02.2020, 13.00 o'clock, APB 1096

Invitation to the presentation of Martin Thuemmler

Topic: Development of a processor pipeline based on RISC-V ISA

Project: Forschung und Entwicklung in der Informatik

Supervisor: Muhammad Ali

Abstract: Computer architecture has made incredible progress over the years. This improvement is from both the technology used to build processors and innovations in processor design. RISC-V is becoming popular nowadays both in academics and in industry. This work investigates RISC-V instruction set architecture (ISA) for the development of computer architecture design. RISC-V is an open-source instruction set architecture based on reduced instruction set computing (RISC) and is developed by the University of California, Berkeley (UCB). RISC-V supports 32-bit and 64-bit architectures, with a promise to support 128-bit architectures in the future. RISC-V also has a free available toolchain and an ISA simulator (called “Spike”). RISC-V allows developers to add custom instructions to its ISA which helps maintain the backward and forward compatibility of the ISA. This characteristic of RISC-V can be used to add instructions that are application-specific to improve performance and accuracy. In this work, the student needs to study RISC-V ISA specification for a 32-bit architecture and underline the basic requirements for the instruction fetch (IF) and instruction decode (ID) pipeline stage for a RISC-V based processor. A state of the art research is required on computer architecture design and optimization techniques used. The student needs to implement the instruction fetch IF, instruction decode ID and a control unit based on design decisions in VHDL. Different optimization techniques (e.g. hazard avoidance techniques, power management techniques, custom instructions, etc.) should be kept in mind when implementing the control unit. It is also required to develop a test bench to verify the functionality of each design. Evaluation of the implemented design should be performed based on execution delay, area, and power consumption. ​