Matthias Nickel: Implementation and optimization of the AKAZE feature detection algorithm for the HiFlipVX library using high-level synthesis (Master Thesis)

20.05.2021, 2:30 pm

Invitation to the final presentation of Matthias Nickel (Master Thesis)

Topic:  Implementation and optimization of the AKAZE feature detection algorithm for the HiFlipVX library using high-level synthesis

Project: Master thesis

Supervisor: Lester Kalms

Abstract: The amount of image data to be processed has been increased repeatedly over the last few decades. One major computer vision task performed on these data is to extract information to find patterns in and between images. Many pattern recognition algorithms to perform feature detection and description to solve this task were proposed. The algorithms to perform these tasks can be quite complex and demanding on computational resources as well as on power consumption. One efficient proposed pattern recognition algorithm is accelerated KAZE (A-KAZE). FPGAs are suitable to meet real-time and power constrains which are required by many applications. The issue is that efficient programming on FPGAs requires quite a knowledge in the area of optimization mythology, resulting in high demands on the required implementation time, even using high-level synthesis tools. HiFlipVX is a high-level synthesis library based on the OpenVX standard to allow to implement computer vision tasks on FPGAs without or little knowledge about FPGAs or high-level synthesis.
This work presents an implementation of the A-KAZE algorithm for Hi-FlipVX. The implementation proposes modifications on library functions and also presents new functions to extend the library. The proposed functions are kept as fine granular and generic as possible to allow them to be reused in other algorithms.

Tests conducted together with the FREAK descriptor on the implementation produced high results in context of the repeatability. Without subpixel refinement a repeatability of 88.4098% in average was achieved. This is just around 3% lower compared to a pure floating point software solution with 91.3775%. Showing that good results in feature detection can also be achieved using just integer data types to represent fractional bits. A comparison using high precision floating point implementation of the subpixel refinement only together with rest of the implementation using either 8 or 16 bits achieved with 90.7339% even closer results. But the subpixel refinement function becomes then also very resource demanding. Together with the streaming fashion processing using linebuffers and sliding windows and the fact that for each implemented function a loop iteration latency of 1 was achieved makes this solution very efficient to be applied on FPGAs.