Ran Bi: Implementation of configurable processing elements for Pooling and Activation for FPGA-Neural Processing Unit (FNPU) (Intermediate presentation project work)

23.06.2023, 08:00 am

Invitation to the intermediate presentation of Ran Bi

Topic: Implementation of configurable processing elements for Pooling and Activation for FPGA-Neural Processing Unit (FNPU)

Project: Project work

Supervisors: Muhammad Ali, Markus Helbig, Lester Kalms

Abstract: Deep Learning Neural Networks (DNNs) are vastly used in the domains of computer vision, natural language, speech recognition, and more. For the past years, DNNs have been a dominant methodology for implementing new learning models. Although DNNs are very efficient and accurate, they are usually very computationally intensive and require a lot of memory resources. There are different domain-specific architectures for DNNs e.g. GPUs, and hardware accelerators. Recently, a trend to use minimalistic specialized instruction set architecture (ISA) for efficient DNN processing has risen, e.g. Tesla FSD, Cambricon. This work focuses on specialized processing elements for a minimalistic ISA for DNN-based algorithms. In the course of the proposed project work, the student should survey the literature for the most commonly used deep learning algorithms e.g. CNNs and specialized instruction set architectures e.g. Google TPU, Cambricon, Tesla FSD, etc. The research should be focused on implementing configurable processing element (PE) targeted for pooling and activation layers. The implemented PE should have configurable functional units based on operation type, size, bit-width, parallelism, etc., and a control flow based on an ISA. The PE should be developed in SystemVerilog and the design should be verified and evaluated. The evaluation should include performance (estimated operations per second), resource utilization, power analysis, and timing analysis.