Rohan Krishna Vijayaraghavan: Implementation of a configurable MAC array for FPGA-Neural Processing Unit (FNPU) (Intermediate presentation project work)

23.06.2023, 08:00 am

Invitation to the intermediate presentation of Mr. Rohan Krishna Vijayaraghavan

Topic: Implementation of a configurable MAC array for FPGA-Neural Processing Unit (FNPU)

Project: Project work

Supervisors: Muhammad Ali, Markus Helbig, Lester Kalms

Abstract: Deep Learning Neural Networks (DNNs) are vastly used in the domains of computer vision, natural language, speech recognition, and more. For the past years, DNNs have been a dominant methodology for implementing new learning models. Although DNNs are very efficient and accurate, they are usually very computationally intensive and require a lot of memory resources. There are different domain-specific architectures for DNNs e.g. GPUs, and hardware accelerators. Recently, a trend to use minimalistic specialized instruction set architecture (ISA) for efficient DNN processing has risen, e.g. Tesla FSD, Cambricon. In the course of the proposed project work, the student should survey the literature for the most commonly used deep learning algorithms, and specialized instruction set architectures (ISAs) e.g. Google TPU, Cambricon, etc. The research should be focused on accelerating convolution and fully connected layers. The student should understand previous works on systolic MAC (Multiply-Accumulate) array and extend the work to use it as a processing element (PE). The PE ISA and control flow should be defined, which should allow controlling the data movement and execution control. The implemented design should be verified and evaluated. The evaluation should include performance (estimated MAC operations per second), resource utilization, power analysis, and timing analysis.