Vimal Raj: Scheduler for a RISC-V based Out-of-Order Processor (Zwischenpräsen­tation Projektarbeit)

08.12.2021, 9:00 Uhr

Einladung zur Zwischenpräsentation von Vimal Raj

Thema: Scheduler for a RISC-V based Out-of-Order Processor

Projekt: Projektarbeit

Betreuer: Muhammad Ali

Abstract: This work investigates a scheduler for out-of-order execution for a RISC-V-based processor. RISC-V is an open-source instruction set architecture developed by the University of California, Berkeley. RISC-V supports 32-bit and 64-bit architectures. RISC-V also has a free available toolchain. RISC-V allows developers to add custom instructions to its ISA which helps maintain the backward and forward compatibility of the ISA. This characteristic of RISC-V can be used to add instructions that are application-specific to improve performance and accuracy. In this work, the student will first investigate different out-of-order execution techniques e.g. register renaming, Tomasulo algorithm, score-boarding, etc. A comparison will be made between different techniques and a suitable technique will be chosen. The chosen technique should be developed based on the RISC-V 64-bit (RV64I) specification. The student also needs to develop other key processor components to have a complete system. A comparison should also be made with related work. Evaluation should be done based on area, power, and performance. Finally, the student needs to document his implementation and findings.