Von Ameln: Evaluating RISC-V Instruction Set Architecture (ISA) w.r.t. Machine Learning

12.11.2019, 10.00 o'clock, APB 1096

Invitation to the presentation of Matthias Von Ameln

Topic: Evaluating RISC-V Instruction Set Architecture (ISA) w.r.t. Machine Learning

Project: Analyse eines Forschungsthemas​

Supervisor: Muhammad Ali

Abstract: This work investigates RISC-V instruction set architecture (ISA) in the area of machine learning. Machine learning algorithms are used for object detection applications and they are becoming more computational intensive by the day. This is a major problem for embedded systems that have critical constraints of area, time, etc. This can be solved by different techniques. The most popular technique is building a hardware accelerator, which is area efficient and provides good performance but it reduces programmability in the architecture. Other popular techniques are adding custom instructions to the processor or adding a co-processor within the architecture, etc. In this work, the student needs to evaluate RISC-V ISA for the techniques mentioned above. RISC-V is an open source instruction set architecture developed by the University of California, Berkeley. RISC-V also has a free available toolchain and an ISA simulator (called “Spike”). RISC-V allows developers to add custom instructions to its ISA which helps maintain the backward and forward compatibility of the ISA. This characteristic of RISC-V can be used to add instructions that are application specific to improve performance and accuracy. The student needs to investigate different ISAs for machine learning and how they can be integrated into RISC-V ISA. Also the student needs to investigate different RISC-V implementations in which they extend the ISA. A custom instruction simulation for a machine learning function (e.g. convolution layer of CNN) needs to be simulated in Spike simulator as a test case and evaluated (code size, estimated time, etc.). For co-processors, RISC-V ISA will be investigated on how it can be integrated with the processor and similar implementations need to be researched and documented.