von Ameln: MSI(-X) for PCIe on a FPGA

11.01.2019, 2:00-3:00 p.m., APB room 1096

This report presents the implementation and evaluation of "Message Signalled Interrupts". There are two constraints. First, the system bus PCIe is used for communication. Second, the application logic is implemented on an Intel Cyclone V FPGA. The primary objective is to reduce the interrupt latency.

After a short introduction of the PCIe architecture, the interrupt specification defined by the PCIe standard is described. In a next step, the design space to implement PCIe on a FPGA is shown. Thereby, the work is embedded into the big picture. Subsequently, the focus is set to the concrete application context. Since the FPGA uses a PCIe IP core, its interfaces are explained. Thereby, the links to the specification are clarified. In the next step, a design is worked out on basis of the previous analysis. Mainly UML diagrams are used to model the behaviour. From the resulting implementation only the important source code snippets are presented. Further, the test procedure is mentioned. Besides the hardware implementation, the OS driver modifications are discussed. To prove the objective, measurements are taken and evaluated. Finally, a conclusion is drawn.