Yifan Yang: RISC-V Processor Development: Cache Memory and Branch Prediction Unit (Intermediate presentation project work)

12.03.2021, 10:00 am

Invitation to the intermediate presentation of Yifan Yang

Topic: RISC-V Processor Development: Cache Memory and Branch Prediction Unit

Project: Projekt work

Supervisor: Muhammad Ali

Abstract: This work investigates cache memory system and a dynamic branch prediction unit (DBPU) for a RISC-V based processor. RISC-V is an open-source instruction set architecture developed by the University of California, Berkeley. RISC-V supports 32-bit and 64-bit architectures. RISC-V also has a free available toolchain. RISC-V allows developers to add custom instructions to its ISA which helps maintain the backward and forward compatibility of the ISA. This characteristic of RISC-V can be used to add instructions that are application-specific to improve performance and accuracy. In this work, the student will first investigate different dynamic branch prediction techniques for embedded processors. A comparison will be made and suitable technique will be chosen and implemented. The student needs to develop cache memory system for instruction memory interface and data memory interface. These cache memories are needed for fast data processing and needs to be integrated in the system. A relevant speedup needs to be evaluated on the cost of hardware used. A comparison should also be made with related work. Evaluation should be done based on area, power and performance. Finally, the student needs to document his implementation and findings.​