Oct 13, 2025
Yong Huang: A Dynamic Multi-Level Signal Selection Framework for Efficient FPGA Debugging (Intermediate presentation master thesis)
13.10.2025, 10:30 am
Invitation to the intermediate presentation of Mr. Yong Huang
Topic: A Dynamic Multi-Level Signal Selection Framework for Efficient FPGA Debugging
Project: Master thesis
Supervisors: Yanjun Lu, Jin Yuan