Chipentwürfe 2011 bis 2015
Inhaltsverzeichnis
Atlas_Chip
MPSoC with two vector DSP cores. Ultra-fast DVFS for dynamic power management. DDR2 memory interface and high-speed serial NoC links with 36 Gbit/s data rate.
![ATLAS_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2011_03_atlas/atlas_chipfoto/@@images/ec7a290c-2017-412b-a2b1-47a34aeadca9.png)
Chipfoto ATLAS_Chip
Technologie | 65 nm CMOS |
Area | 7,4 mm² |
Tape-Out | 03_2011 |
Publikationen |
DOI: 10.1109/ISSCC.2012.6176902 |
DNC-2_Chip
Second generation of the high-speed pulse transmission and routing chip for the first-generation BrainScales waferscale system. Hosts 8 serial LVDS links to neuromorphic chips and one multi-lane FPGA interface for a total throughput of 32Gbit/s.
![Chipfoto DNC2, Chip-on-Board](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2011_05_DNC2_CoB.jpg/@@images/dafbe81e-1c8d-4016-92a8-a6142c964c1c.jpeg)
Chipfoto DNC-2 (Chip-on-Board)
Technologie | 180 nm CMOS |
Area | 50 mm² |
Tape-Out | 05_2011 |
MAPLE_Chip
Neuromorphic chip with 16 neurons and 512 synapses operating at a speed-up of 10000, realized in OTA-C circuit technique. Features short-term plasticity and local correlation plasticity (LCP) rule for long-term learning.
![MAPLE_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2011_07_maple/MAPLE_chipfoto.png/@@images/f633fdea-d3f3-4515-bf1c-9f9a96907243.png)
Chipfoto MAPLE_Chip
Technologie | 180 nm CMOS |
Area | 4,5 mm² |
Tape-Out | 07_2011 |
Cool28_SoC
Component test chip for standard cells, high-speed IO cells, and SRAM macros developed at HPSN. Tensilica DSP with adaptive voltage and frequency scaling (AVFS) and corresponding ADPLL clock generator.
![Cool28, System-on-Chip, Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2012_07_cool28_soc1/Cool28SoC1_chip.jpg/@@images/5e8f659f-52c5-49bb-92b5-9b2d35b26b5c.jpeg)
Chipfoto, Cool28_SoC
Technologie | 28 nm CMOS |
Area | 2,25 mm² |
Tape-Out | 7_2012 |
Publikation | DOI: 10.1109/TCSII.2013.2278123 |
Delta-Sigma-ADC
Cooperation with former ZMDI to investigate high resolution incremental delta-sigma ADCs for DC-input signals. It contains two hybrid ADCs with current input and 3 discrete time ADCs with modulators of 3rd and 4th order. The main part of the chip area is filled with photo-diode test structures to evaluate spectral sensitivity of this technology.
![DS_ADC_chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2012_10_delta_sigma_adc/DS_ADC_chip.JPG/@@images/c2beda0f-f0c3-40d5-a4ab-cf1c964fadbe.jpeg)
Chipfoto Delta-Sigma-ADC
Technologie | 180 nm CMOS |
Area | 25 mm² |
Tape-Out | 10_2012 |
Publikationen | DOI: 10.1109/ECCTD.2013.6662252 DOI: 10.1109/ISCAS.2013.6572081 DOI: 10.1109/ICECS.2013.6815476 |
TITAN
Testchip with ADPLL, SAR ADC and serial NOC links. Also includes a neuromorphic array with 64 neurons and 8192 plastic synapses and circuits for high resolution on-chip IR measurement. 12 bit 4 MSamples/s SAR ADC with configurable redundancy.
![Titan-Chip, Novemner 2012, 28nm](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2012_11_Titan_HPSN_part.jpg/@@images/109ed5c8-4448-4c30-99b2-ac2b2379f627.jpeg)
Chipfoto Titan (Multiproject-Chip; eigener Anteil)
Technologie | 28 nm CMOS |
Area | 4,5 mm² |
Tape-Out | 11_2012 |
Publikationen | DOI: 10.1109/JSSC.2014.2381637 DOI: 10.1109/TBCAS.2014.2379294 |
Tomahawk_2
Heterogeneous MPSoC with 8 Duo processing elements for software defined radio. Fine-grained power management via DVFS. On-chip serial links with up to 72 Gbit/s, DDR2 and FPGA interfaces for off-chip communication.
![TOMAHAWK2_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2012_11_tomahawk-2/TOMAHAWK2_chip.jpg/@@images/54ac5166-d472-4286-a12f-6deecea208b4.jpeg)
Chipfoto Tomahawk_2_Chip
Technologie | 65 nm CMOS |
Area | 36 mm² |
Tape-Out | 04_2013 |
Publikation | DOI: 10.1109/ISSCC.2014.6757394 |
BIONECT_Chip
Neuromorphic chip with 320 neurons for real-time coupling with neural tissue. Contains 1600 conductance-based multi-synapses, enabling emulation of up to 320000 single synaptic connections. Realized in switched-capacitor circuit technique. Short-term plasticity circuits on chip as well.
![BIONECT_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2013_12_bionect/BIONECT_chip.jpg/@@images/52211507-46d4-49fb-a16e-a5bb8228dbbf.jpeg)
Chipfoto BIONECT_Chip
Technologie | 180 nm CMOS |
Area | 50 mm² |
Tape-Out | 12_2013 |
Blizzard_Chip
On-chip DC-DC voltage converter and Tensilica Xtensa DSP with adaptive power management. 10bit 16MS/s SAR ADC with window functionality and PWM signal generator with 62.5ps timing resolution for fast changes of operation modes and high power efficiency.
![BLIZZARD_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2014_01_blizzard/BLIZZARD_chip.JPG/@@images/d3c5a2ea-c95a-4304-b4fd-4546d2e19e23.jpeg)
Chipfoto BLIZZARD_Chip
Technologie | 28 nm CMOS |
Area | 4 mm² |
Tape-Out | 01_2014 |
Publikationen | DOI: 10.1109/ISCAS.2015.7168989 DOI: 10.1007/s10470-015-0591-2 |
TITAN_3D
Testchip for energy efficient TSV transceiver for 3D chip stacking achieving 50 fJ/Bit at 8 Gbit/s. Flip chip package and custom silicon interposer with redistribution layer. LX5 Tensilica core with instruction set extension optimized for database query processing.
![TITAN3D_Chip_n_Board](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2014_04_titan3d_cob/TITAN3D_COB.jpg/@@images/f0a11f70-0bc0-45bb-9f4a-5d86557ad186.jpeg)
TITAN_3D_Chip_on_Board
Technologie | 28 nm CMOS |
Area | 4,5 mm² |
Tape-Out | 04_2014 |
Publikationen |
DOI: 10.1007/978-3-319-20481-9_3 |
Tomahawk DBA
Heterogeneous MPSoC with 4 Tensilica ASIPs for database query processing. NoC with 80 Gbit/s serial link. 2 LPDDR2 memory interfaces and off-chip FPGA interface with 5 Gbit/s SerDes links.
![TOMAHAWK_DBA_Chip on Board](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2014_10_tomahawk-dba/TOMAHAWK_DBA_CoB.jpg/@@images/469ebaaf-ff2c-43d1-bd7d-907533edd60e.jpeg)
Tomahawk_DBA_Chip_on_board
Technologie | 28 nm CMOS |
Area | 18 mm² |
Tape-Out | 10_2014 |
Publikation | DOI: 10.1145/2897937.2897986 |
Nanolink_65
Testchip for the serial communication links of the neuromorphic BrainScales wafer-scale system within the Human Brain Project (HBP). It contains 2 source-synchronous serial links for chip-to-FPGA communication at data rates up to 2GBit/s.
![IC NanoLink 65 im Gehäuse](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2014_10_NanoLink65_package.jpg/@@images/9c5d48eb-b784-45dd-bfa9-f38c2a0aa409.jpeg)
NanoLink65_CiP
Technologie | 65 nm CMOS |
Area | 2,5 mm² |
Tape-Out | 10_2014 |
Nanolink_28
Testchip for the serial communication links of the neuromorphic many-core system Spinnaker2 within the Human Brain Project (HBP). It contains 2 multi-standard SerDes PHYs with data rates up to 5GBit/s.
![NANOLINK28_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2014_12_nanolink28/NANOLINK28_chip.png/@@images/3a10bddb-7077-4249-8317-29ea2be95e25.png)
Chipfoto NanoLink_28
Technologie | 28 nm CMOS |
Area | 2 mm² |
Tape-Out | 12_2014 |
Santos
Heterogeneous MPSoC with 4 Duo-PEs and fine-grained power management. OpenMSP430 core with timing detection flip-flops for resilient low-power operation in all process corners. ADPLLs enable NoC with GALS clocking scheme and are used as an entropy source for true random number generation.
![Santos, Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2015_07_santos/Santos_chip.jpg/@@images/ee930efc-81be-4f84-8c76-dadada5bf7b1.jpeg)
Chipfoto, Santos
Technologie | 28 nm CMOS |
Area | 18 mm² |
Tape-Out | 07_2015 |
Publikation | DOI: 10.1145/3061639.3062188 |
<-2006 - 2010 | 2016 - 2020 -> |