Chipentwürfe 2006 bis 2010
Inhaltsverzeichnis
Active-Pixel-Sensor 65
Active sub-100nm pixel image sensor with photo diodes in varying depths in the substrate (116*128 and 48*96 pixels). Also used as a test chip for Delta-Sigma modulator, pipeline ADC, and pixel matrix readout.
![APS65_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2006_active-pixel_aps65/aps65_chipfoto/@@images/dfb298ff-797f-4e39-828a-9f85dab2636a.png)
Chipfoto Active-Pixel-Sensor 65
Technologie | 65 nm CMOS |
Area | 1,08 mm² |
Tape-Out | 01_2006 |
Tomahawk 1
Heterogeneous MPSoC for SDR applications. Complete backend implementation at HPSN.
Technologie | 130 nm CMOS |
Area | 100 mm² |
Tape-Out | 03_2007 |
Publikation | DOI: https://doi.org/10.1109/ESSCIRC.2008.4681893 |
PIXSTACK
High-Speed Image Sensor with 320x240 Pixel cells. Grayscale image with 8bit resolution and 500 frames/s. Power consumption of 50mW at 3.3V supply voltage.
![Pixstack, 2007, Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2007_PIXSTACK_chip.jpg/@@images/550cc0d7-52f5-43f9-bd88-f0ba7f718a4a.jpeg)
Chipfoto, Pixstack
Technologie | 0,35 µm CMOS |
Area | 20 mm² |
Tape-Out | 06_2007 |
MiniLink
Minilink is series of prototype chips for application-specific digital neuromorphic communication. They contain multiple LVDS source synchronous transmission links, 1GHz PLL and bias generation.
![MINILINK_1_layout_2](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2007_07_minilink_1/minilink_1_layout_2/@@images/1cd63c62-9ede-4664-896b-94be943c821e.jpeg)
Layout MiniLink_1
Technologie | 180nm CMOS |
Area | 4,5 mm² |
Tape-Out | 06_2007 |
![MINILINK_2_Chip on Board](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2008_01_minilink_2/minilink_2_chip-on-board/@@images/06021c99-dfde-4fb2-9da0-4ca4b3af9391.jpeg)
MiniLink_2 Chip_on_Board
Technologie | 180nm CMOS |
Area | 2,25 mm² |
Tape-Out | 01_2008 |
![MINILINK_3_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2008_04_minilink_3/minilink_3_chipfoto/@@images/54f6ec7f-9450-402d-b2f0-fde5652ba8ab.jpeg)
Chipfoto MiniLink_3
Technologie | 180nm CMOS |
Area | 2,25 mm² |
Tape-Out | 04_2008 |
![MINILINK_4_Chipfoto_Chip on Board](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2008_06_minilink_4/minilink_4_chipfoto_chip-on-board/@@images/d5e3b16a-0e74-4997-961c-c4e835810ef5.jpeg)
MiniLink_4 Chip_on_Board
Technologie | 180nm CMOS |
Area | 4,5 mm² |
Tape-Out | 06_2008 |
Minilink- Publikationen |
DOI:10.1016/j.vlsi.2011.05.003 DOI: 10.3389/fnins.2011.00117 |
AFE_Chip
Programmable gain amplifier (PGA) and Delta-Sigma modulator (DSM) for automotive applications. The DSM is realized in switched-capacitor in a MASH 2-1-1 structure. Also incorporates student-designed OTA circuits.
![AFE_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2008_08_afe/afe_chipfoto/@@images/2a03488d-5894-4ae6-a80b-db7e9a662fe6.jpeg)
Chipfoto AFE_Chip
Technologie | 0,6 µm CMOS |
Area | 21,16 mm² |
Tape-Out | 08_2008 |
Publikation | https://ieeexplore.ieee.org/document/5551697 DOI: 10.1109/ICECS.2009.5410940 |
DNC_Chip
High-speed pulse transmission and routing chip for the first-generation BrainScales waferscale system. Hosts 8 serial LVDS links to neuromorphic chips and one multi-lane FPGA interface for a total throughput of 32Gbit/s.
![DNC_Chipfoto](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2008_11_dnc/DNC_chipfoto.png/@@images/9391160d-9f41-4113-81d3-f690a22b974f.png)
Chipfoto DNC_Chip (Detail)
Technologie | 180 nm CMOS |
Area | 50 mm² |
Tape-Out | 11_2008 |
Publikationen |
www.sciencedirect.com/../article/../S0167926011000538 |
TOMMY_Chip
MPSoC with MIMO sphere decoder and FEC for mobile baseband processing. GALS clocking using 8 ADPLLs, packet-oriented NoC, and LVDS FPGA interface.
![TOMMY_Chipfoto im package](https://tu-dresden.de/ing/elektrotechnik/iee/hpsn/ressourcen/bilder/chipgallery/2010_03_01_tommy/TOMMY_package.png/@@images/287f86a4-64d8-47f7-be65-03c9bfc0d8e6.png)
Chipfoto TOMMY_Chip (im Package)
Technologie | 65 nm CMOS |
Area | 7,4 mm² |
Tape-Out | 03_2010 |
Publikationen |
DOI: 10.1109/ISSCC.2012.6176981 |
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