Statusvortrag im Promotionsver­fahren von Frau Ensieh Aliagha

Abstract: 

With the widespread use of portable devices like smartphones, wearable, and other IoT devices, the energy-efficient design of accelerators is becoming increasingly vital. These devices run on batteries, and lower energy consumption translates to longer battery life. Signal processing applications constitute some of the most widely used workloads on portable devices. Given the rapidly evolving nature of signal processing workloads, fixed‑function ASIC accelerators lack the flexibility required to support new applications with differing requirements. Accordingly, reconfigurable architectures, such as FPGAs and coarse‑grained reconfigurable architectures (CGRAs), address this by allowing hardware configurations to be updated in the field, effectively bridging the gap between performance and adaptability. As a result, reconfigurability and energy efficiency emerge as the two important criteria for the accelerator targeting the signal processing domain. In this work, we explore key architectural components, processing element design, memory hierarchy organization, interconnect topologies, and power management of the accelerator. Our objective is to improve energy efficiency while maintaining flexibility to accommodate future application developments.