Muhammad Ali, M. Sc.
© Muhammad Ali
Wissenschaftlicher Mitarbeiter
NameHerr Muhammad Ali , M.Sc.
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Short CV:
Muhammad Ali is a Ph.D. student and assistant researcher in Computer Science in the Adaptive Dynamic Systems (ADS) research group at the Technical University in Dresden(TUD), Germany, since July 2018. Before joining the research group, he studied Electrical Engineering at National University of Sciences and Technology, Islamabad, Pakistan, where he received his Bachelor’s degree in 2013. He completed his Master's degree in Embedded Systems from Technical University of Chemnitz in December 2017.
Research Interests:
His current research interests include RISC-V and ASIP for machine learning.
Publications:
2025
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Towards Complete Open-Source Environments: FPGA-Based GPU Overlay Controlled by RISC-V, Okt. 2025, Architecture of Computing Systems - 38th International Conference, ARCS 2025, Proceedings. Tomforde, S., Krupitzer, C., Vialle, S., Suarez, E. & Pionteck, T. (Hrsg.). Springer Science and Business Media B.V., S. 94-108, 15 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Konferenzband
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P-CORE: Exploring RISC-V Packed-SIMD Extension for CNNs, Aug. 2025, in: IEEE access. 13, S. 146603-146616, 14 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Fachzeitschrift > Forschungsartikel
2023
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Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-based Approach to Simulation and Modeling, Juli 2023, Embedded Computer Systems: Architectures, Modeling, and Simulation: 23rd International Conference, SAMOS 2023, Samos, Greece, July 2–6, 2023, Proceedings. Silvano, C., Reichenbach, M. & Pilato, C. (Hrsg.). Springer, Cham, S. 269–282, 14 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Konferenzband
2022
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Application Specific Instruction-Set Processors for Machine Learning Applications, 2022, FPT 2022 - 21st International Conference on Field-Programmable Technology, Proceedings. Institute of Electrical and Electronics Engineers (IEEE), 4 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Konferenzband
2021
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A Parametrizable High-Level Synthesis Library for Accelerating Neural Networks on FPGAs, Mai 2021, in: Journal of Signal Processing Systems. 93, 5, S. 513-529, 17 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Fachzeitschrift > Forschungsartikel
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AITIA: Embedded AI Techniques for Embedded Industrial Applications, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL). Institute of Electrical and Electronics Engineers (IEEE), S. 374-375, 2 S.Elektronische (Volltext-)VersionPublikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Konferenzband
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Power-Aware Computing Systems on FPGAs: A Survey, 2021, S. 45-51, 7 S.Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
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Vector processing unit: A RISC-V based SIMD Co-processor for Embedded Processing, 2021, S. 30-34, 5 S.Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
2020
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AITIA: Embedded AI Techniques for Embedded Industrial Applications, 2020, S. 1-7, 7 S.Elektronische (Volltext-)VersionPublikation: Beitrag zu Konferenzen > Paper
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Domain Adaptive Processor Architectures, 2020, Kommunikation und Bildverarbeitung in der Automation. Neuerscheinung Aufl., Berlin, Heidelberg, Band 12. S. 315-330, 16 S.Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten > Beitrag in Buch/Sammelband/Gutachten