Christoph Tietz: Realization of a 2D-Bitstream Relocation on Xilinx UltraScale+ (Presentation Belegarbeit)

30.04.2021, 10:00 am

Invitation to the presentation of Mr. Christoph Tietz

Topic:  Realization of a 2D-Bitstream Relocation on Xilinx UltraScale+

Project: Belegarbeit

Supervisor: Najdet Charaf

Abstract: Partial reconfiguration is a technique to reconfigure Xilinx FPGAs partly while the rest keeps running. This allows a very great flexibility. However, this comes with additional costs. The number of partial bitstreams which need to be generated is the product of the number of reconfigurable modules and reconfigurable partitions. This occupies a lot of memory resources and significantly increases the design time. To reduce those disadvantages a technique called bitstream relocation can be used. Based on an internally developed design flow at the institute, this thesis extends its features: Front-end functions are implemented to allow the usage of different design sources. An automated VHDL creator is implemented to facilitate the creation of recurring hardware descriptions required by the design flow. Moreover, the isolation design flow is now integrated to avoid Feed-Through paths, which is an important requirement for relocatable bitstreams. In order to enable the relocation design flow for UltraScale+ FPGAs, feasibility is investigated by low level analysis of bitstream data. Based on this, applications are implemented to facilitate the bitstream relocation for those FPGAs. Furthermore, an extension to the design flow is developed that allows bitstream relocation of half-clock regions. This thesis shows how different design sources like block designs or IP cores can now be integrated into the design flow as well as successful bitstream manipulation tools for 2D bitstream relocation on Xilinx UltraScale+ FPGAs.