Cornelia Wulf: A Virtualization Layer for the Management of Hardware Tasks in Embedded Reconfigurable Systems (Statusvortrag)

05.12.2022, 08:30 Uhr, Raum APB 1004

Einladung zum Statusvortrag im Promotionsverfahren von Frau Dipl.-Inf. Cornelia Wulf

Thema: A Virtualization Layer for the Management of Hardware Tasks in Embedded Reconfigurable Systems

Betreuerin: Prof. Dr. Diana Göhringer

Fachreferent: Prof. Dr. Wolfgang Nagel

Abstract: Virtualization of embedded systems plays an increasingly important role. The consolidation of multiple systems onto the same hardware platform reduces the hardware footprint, increases reliability and scalability, and the abstraction of the underlying hardware leads to a faster time-to-market. The utilization of FPGAs offers embedded systems the opportunity to exploit the FPGA’s parallelism, reconfigurability, and energy saving potential. Nevertheless, FPGAs are not conceptualized for shared usage. So, FPGA virtualization poses the challenge to adhere with data and performance isolation. The limited FPGA area and high reconfiguration times impede the shared usage of reconfigurable resources.

This work addresses the research questions how to conquer the limitations of embedded reconfigurable systems, how to ensure isolation and how to meet varying requirements of diverse applications. We present an FPGA virtualization layer that can be tailored to the specific needs of the respective embedded system. In order to give virtual machines access to hardware accelerators, we depict a POSIX Threads-based frontend/backend driver mechanism and an MMU-based mechanism. In embedded systems, often small and efficient real-time operating systems, e.g., for safety-critical control systems, run next to general purpose operating systems that offer consumer functionality. So, our virtualization layer improves area utilization and reconfiguration latencies by means of a dynamic scheduling strategy that considers hard, soft, and no real-time requirements of hardware tasks. We extend our strategy to FPGA clusters with a special focus on systems that require high reliability. In order to improve energy efficiency, we synchronize hardware tasks, which leverages the use of a power gating mechanism for flash-based FPGAs. The adaptation of the synchronization strategy for SRAM-based FPGAs is envisaged. Future work includes the virtualization of a network-on-chip to facilitate communication between hardware tasks.