Florian Schuster: Development of a 64-bit RISC-V based multi-core shared memory system (Studienarbeit)

16.04.2021, 14:00 Uhr

Einladung zur Präsentation von Herrn Florian Schuster

Thema: Development of a 64-bit RISC-V based multi-core shared memory system

Projekt: Studienarbeit

Betreuer: Ahmed Kamal

Abstract: The open-source and free-to-use instruction set architecture (ISA) from Berkeley, namely RISC-V, gains traction in every field of computer science. New processor cores implementing this ISA are rapidly emerging around the online community. However, the micro architectural decisions during the design process of computing cores are not the only essential details in processor design because systems with only a single core are rarely relevant these days. State of the art are multi-core systems that can take on complicated and exhausting computing problems. This work’s content shows the creation of such scalable multi-core implementation, based on the RISC-V ISA, a centralized shared memory architecture, and local scratchpad-memories for every processing core. A parallel programming approach is created in addition to the system itself, including a custom linker script and an extensive tool flow, to enable an easy way to write software for the designed architecture. Finally, benchmarking programs were created to estimate the quadcore architecture’s performance on a field programmable gate array (FPGA)
development board.