Julian Haase: Simulation and Modelling of Secure, Reliable and Reconfigurable Network-on-Chip Many-Core Architectures (Statusvortrag)

27.02.2024, 11:00 Uhr, Raum APB 1096

Einladung zum Statusvortrag im Promotionsverfahren von Herrn Dipl.-Ing. Julian Haase

Thema: Simulation and Modelling of Secure, Reliable and Reconfigurable Network-on-Chip Many-Core Architectures

Betreuerin: Prof. Dr. Diana Göhringer

Fachreferent: Prof. Akash Kumar

Abstract: The emerging complexity of many-core architectures has necessitated the evolution of Networks-on-Chip (NoC), which are crucial for maintaining efficient inter-core communication. The development of NoCs for such systems on embedded devices, especially FPGAs, are challenging due to the wide range of design parameters and a fine balance between performance optimization and resource constraints.  While FPGAs are flexible, they have limited resources compared to larger hardware, so developers must make critical decisions about how to best utilize these resources for efficient NoC implementation. In addition, the dynamic nature of data traffic in embedded systems requires a design approach that can adapt to changing conditions without compromising performance or consuming excessive power. The aim of this work is to create a comprehensive simulation platform that bridges the gap between simulation and the realization of such NoC many-core architectures in the early design phase. The focus here is particularly on concepts, investigations and analysis into the security of communication, reliability, and the reconfiguration of parts in the modelled system. The combination of these methods is important to understand the impact and benefits of such architectures, enabling more versatile and customizable hardware designs in the future. In the status talk, I will present my current state. Firstly, the simulation platform for NoC architectures will be discussed. Secondly, the talk delves into methodologies for embedding security protocols within NoC, addressing the growing concerns of data integrity and protection against malicious attacks. The third focus is on the modelling of dynamic reconfiguration of these architectures, facilitating adaptive features in response to varying computational demands and workloads.