08.03.2021
Kun Qin: Extending execution stage of a RISC-V based processor (Zwischenpräsentation Projektarbeit)
12.03.2021, 10:00 Uhr
Einladung zur Zwischenpräsentation von Kun Qin
Thema: Extending execution stage of a RISC-V based processor
Projekt: Projektarbeit
Betreuer: Muhammad Ali
Abstract: This work investigates RISC-V instruction set architecture (ISA) extensions for extending the functionality of the processor. RISC-V is an open-source instruction set architecture developed by the University of California, Berkeley. RISC-V supports 32-bit and 64-bit architectures. RISC-V also has a free available toolchain. RISC-V allows developers to add custom instructions to its ISA which helps maintain the backward and forward compatibility of the ISA. This characteristic of RISC-V can be used to add instructions that are application-specific to improve performance and accuracy. In this work, the student will investigate M-extension and F-extension of the RISC-V ISA. M-extension is to add multiply and divide instructions to the processor. And F-extension is for adding support of single-precision floating-point operations. The student needs to investigate the specification of M- and F- extension from RISC-V and implement a modular extension. For functional verification corresponding test benches needs to be developed. The implementation should be compared with related work. Evaluation should be done based on area, power and performance. Finally, the student needs to document his implementation and findings.