01.07.2024
Muhammad Ali: Methods for Designing and Optimizing Processors for Neural Networks (Statusvortrag)
08.07.2024, 09:30 Uhr, Raum APB 1096
Einladung zum Statusvortrag im Promotionsverfahren von Herrn Muhammad Ali
Thema: Methods for Designing and Optimizing Processors for Neural Networks
Betreuerin: Prof. Dr.-Ing. Diana Göhringer
Fachreferent: Prof. Dr. Akash Kumar
Abstract: With the advancement in machine learning algorithms like Neural Networks (NNs) for object detection or data prediction, a rise in algorithmic complexity is observed. The increase in algorithmic intricacy and the application scenarios results in higher computation demands of embedded systems. NNs are very popular because of their high accuracy but they have high computation and memory requirements. For a general-purpose Central Processing Unit (CPU), these requirements are difficult to meet in time-critical or energy-constrained environments. One way to improve the performance and efficiency of a CPU is to add application-specific instructions to form an Application Specific Instruction-set Processor (ASIP). On the other hand, as RISC-V emerges as an open-source Instruction Set Architecture (ISA), there is a notable surge in both academic and industrial adoption of processor design implementations. Various application domains are being targeted for computer architecture leveraging the RISC-V ISA, ranging from low-power Internet of Things devices to High Performance Computing systems. RISC-V supports 32-bit, 64-bit, and 128-bit architectures and allows the addition of custom instructions for backward and forward compatibility. This work focuses on RISC-V based ASIP architecture that explores different standard and non-standard extensions for NNs. For fast prototyping, ISA extension design space exploration (DSE), and multiprocessor system-on-chip (MPSoC) realization at early stage, simulation platforms are proposed for RISC-V based architectures. For profiling RISC-V extensions and estimate DSE of ISA subsets a profiler tool called RV-ProViler is proposed. An open-source RISC-V Virtual Prototype (VP) platform is extended for DSE of Packed-SIMD operations and MPSoC architectures to explore flexibility and configurability of the system based on application requirements. From the hardware perspective, this work focuses on a RV32IM base RISC-V implementation with optional support for standard extensions; F-extension (floating point), P-extension (Packed-SIMD), and a sub-set of V-extension (Vector operations). The DSE of these extensions with respect to CNN functions shows notable benefits of each specification. A non-standard extension called NN-extension is also an optional support. This focuses on scalar functional units for NN kernels and matrix multiplication instruction to optimize the computation of NNs. The work also focuses on scalability and how based on the scenario or application a SoC or MPSoC can be realized both as a simulation or hardware platform.