Paul Gotschaldt: Exploration of Novel RISC-V based SoC for Robotic (Analysis of a research project)

01.07.2021, 14:00 pm

Invitation to the presentation of Paul Gotschaldt

Topic: Exploration of Novel RISC-V based SoC for Robotic

Project: Analysis of a research topic

Supervisors: Ariel Podlubne, Ahmed Kamaledin

Abstract: RISC-V is a rising instruction set architecture (ISA) that is unlike most other ISA’s provided under an open source license that doesn’t require fees. Having all of the intrinsics publicly available makes RISC-V a great solution in terms of security, scalabilty, stability and extenabilty, especially in the field of embedded devices. Therefore, the ETH Zurich started a collaboration with the University of Bologna regarding a Parallel Ultra Low Power platform targeting high energy efficiency meant to be used by other research institutes, universities, and companies. The platform includes a variety of different RISC-V cores like Riscy or Zero-riscy, a rich set of supported peripherals like I2C, SPI or GPIO and complete SoCs like the single-core microcontroller PULPissimo and PULPino, the multi-core IoT processor OpenPULP and the multi-cluster heterogeneous accelerator Hero. In this thesis, the single-core microcontroller PULPissimo was explored to lay the basis for future projects that utilizes this SoC. The thesis ported the existing PULPissimo to the Pynq and Zedboard and extended the exisiting microcontroller architecture to be
able to communicate with the host processor. Further, the integration of a simple hardware accelerator was realised and a small performance comparsion against a pure software based solution was evaluated.