Complex training period processor design

Lecturer / contact:
Dipl.-Inf. P. Genßler

Component of the following modules:
INF-04-KP, INF-MA-PR, INF-VERT5, IST-05-KP

Frequency:
The course takes place in winter semester and in summer semester.

Time and place:
Please take time and place from the teaching offer catalogue of the faculty informatics.

Contents and qualification aims:
Improvement of knowledge on computer architecture and system design is strived. The objective is the design and implementation of a simple embedded system based on a (simple) MIPS or other processor core. The implementation is done with the help of the hardware description language VHDL for an Altera Cyclone III FPGA. Using a C-test program, the correct function of the system has to be proven on the FPGA board Altera DE0.
For the hardware design, tools from Altera are available. For the software design, a compiler and a dissambler are made available. Also provided are single components of the system: hardware modules for the on-chip RAM and I/O components, as well as the C test application.
Table of contents:
- Introductory seminar on the design task and its realization on a FPGA.
- Autonomous familiarization with the MIPS or any selected microprocessor.
- Design of a concept for the selected microprocessor.
- Implementation of the processor core in VHDL including testbenches for single components and there composition by simulation.
- Assembly of the whole system, test using simulation as well as execution of the C test application on the FPGA board.

References:
- Laboratory manuals: notes on the processor design, MIPS instruction set description, usage manuals for the design tools, documentation of the FPGA board, source code for selected components.
- Patterson; Henessy: Rechnerorganisation und -entwurf, 3. Auflage, 2005 (available in SLUB)
- Henessy; Patterson: Computer architecture a quantitative approach, 2007, mehrbändig (available in SLUB)
- MIPS RISC architecture R2000 / R3000 (A) (available in SLUB)
- Kesel; Bartholomä: Entwurf von digitalen Schaltungen und Systemen mit HDLs und FPGAs, 2. Auflage, 2009 (available in SLUB)
- Keating; Bricaud: Reuse Methodology Manual for System-on-a-Chip Designs, 3rd Edition, 2007, Springer

Type of course:
Complex training

Temporal extend:
 2SWS (1 SWS = 45 minutes per week)

Basic knowledge desired:
basic knowledge hardware programming with VHDL

Final achievement:
- Course paper providing a detailed documentation on the processor design,
- VHDL source code for designed components and test benches,
- C source code for test application,
- Demonstration of the implemented system.