IC designs from 2021
Table of contents
semantIC
Low-power SoC for industrial field devices with a hardware engine for processing the OPC UA communication protocol. The system also includes a RISC-V CPU, a tri-mode Ethernet MAC, and serial peripherals.
Chipfoto semantIC
| Technology | 22 nm FDSOI |
| Area | 4 mm² |
| Tape-out | January 2021 |
| Publication | DOI: 10.1109/TVLSI.2021.3117401 |
LOTUS
Analog/mixed-signal front end for bidirectional interfacing (recording and stimulation) of neuronal tissue, featuring spike detection and compression circuits. 64-channel, 9-bit DSM acquisition; 8-channel, 6-bit current-mode stimulation. (LOTUS stands for:Low-VOltageCircuit Technologies for Ultra-Low-PowerMixed-Signal Systems)
Screenshot Design and Foto des montierten Chips
| Technology | 22 nm FDSOI |
| Area | 10.65 mm² |
| Tape-out | March 2021 |
| Publications | DOI: 10.1109/TBCAS.2022.3142987 DOI: 10.1109/A-SSCC56115.2022.9980793 DOI: 10.1109/NEWCAS57931.2023.10198056 |
SpiNNaker2
The SpiNNaker2 Chip is a 152 core processing chip that will be used to construct the cloud-scale neuromorphic supercomputer SpiNNcloud. It continues the journey from the SpiNNaker1 system/chip in Manchester (https://en.wikipedia.org/wiki/SpiNNaker), with TU Dresden and University Manchester teaming up for this significantly more advanced design. It contains 152 ARM M4F cores, plus various custom accelerators for deep neural networks, spiking neural networks, stochastic computing (e.g. Monte Carlo exploration), etc. It uses advanced power saving features such as adaptive body biasing (supplied by our spinoff company Racyics), event-driven voltage and frequency scaling, energy proportional communication links, and so on. It is the ultimate development in bio-inspired computing coming out of the 10-year EU flagship Human Brain project, and will serve as a research vehicle for large-scale, real time AI, bio-inspired computing and computational neuroscience/brain simulation. It is currently the largest chip&system for real-time brain simulation. The chip has been fabricated by Global Foundries in their 22FDX technology, in a full-mask tapeout. It contains approximately 1.5 Bio transistors. The final SpiNNcloud machine will contain 10^14 transistors, which is incidentally the number of synapses in the human brain...
Again, fun fact: The mirrored rectangle visible in the package photo is actually the SpiNNaker2 chip from the back side.
SpiNNaker2
| Technology | 22 nm FDSOI |
| Area | 103 mm² |
| Tape-out | June 2021 |
| Publications | DOI: 10.1109/OJCAS.2026.3714974 doi.org/10.48550/arXiv.2103.08392 doi.org/10.48550/arXiv.2401.04491 |
powerlink IC
100M Ethernet PHY and MAC with control circuitry for power-over-dataline. Embedded FPGA with a 12x12 tile array. Ultra-low-power standalone sensor signal classification module for ECG and gesture classification and speech wake-up. Energy-efficient 32-bit RISC-V processor enabled by a 0.55 V supply and adaptive body bias.
Chipfoto, powerlink-IC
| Technology | 22 nm FDSOI |
| Area | 4 mm² |
| Tape-out | November 2021 |
| Publication | DOI: 10.1109/ISOCC59558.2023.10396509 |
ORCA
SoC for keyword spotting with a streaming interface from an I2S microphone. Audio preprocessing using a mel-frequency cepstral coefficient (MFCC) accelerator and classification with flexible sparse RNN accelerator. Speech-wake-up with an ultra-low-power, stand-alone sensor signal classification module. Additional components: 32-bit RISC-V processor, embedded FPGA, capacitive DC/DC converter.
| Technology | 22 nm FDSOI |
| Area | 3.24 mm² |
| Tape-out | September 2022 |
| Publication | DOI: 10.1109/AICAS57966.2023.10168587 |
ORCA-Test-PCB
SYNCH
SYNCH is a first-of-its-kind neural recording and stimulation interface, featuring powerful hardware accelerators and a processor to fully integrate signal processing and classification capabilities. Developed in 22 nm FDSOI, this programmable system-on-chip represents a milestone in energy efficiency, towards fully implantable cortical neuroprostheses.
Chipfoto, SYNCH-IC
| Technology | 22 nm FDSOI |
| Area | 9 mm² |
| Tape-out | November 2022 |
| Publication | journals/neuroscience/articles/10.3389/ |
Iceberg
The ICEBERG-IC served as a platform for a diverse set of experimental circuits designed and implemented by PhD students at HPSN. Among others, a low-power neural learning unit for edge and IoT applications and a GRU-based classifier of neuronal firing dynamics observed in vitro in Multi-Electrode Arrays (MEAs) were successfully implemented.
Chipfoto Iceberg-IC
| Technology | 22 nm FDSOI |
| Area | 2 mm² |
| Tape-out | December 2023 |
| Publications |
ORCA2
Updated ORCA for machine bearing fault detection from accelerometer and microphone data. Interface for multiple parallel input channels and pre-processing by parallelized MFCC computation. Flexible sparse RNN accelerator for classification. Both were developed as part of the Scale4Edge project.
| Technology | 22 nm FDSOI |
| Area | 1.94 mm² |
| Tape-out | November 2024 |
IC-Layout ORCA2
EVENTS-IC
Edge chip for real-time image processing for livestock monitoring, including accelerators for sparse convolutional neural networks (CNN), event-based recurrent neural networks (RNN), as well as a Cadence DSP core.
| Technology | 16 nm FinFET |
| Area | 6.45 mm² |
| Tape-out | April 2025 |
| Publication | (preprint) DOI:10.48550/arXiv.2607.26835 |
ENENTS-IC, Chipfoto
SEMECO
A highly integrated AI System-on-Chip (AI-SoC) for a psychoadaptive, multisensory communication implant.
While individuals with normal hearing can effortlessly perform attention-guided source separation for active listening, hearing-impaired patients often struggle in complex acoustic environments, significantly impacting their social interactions and quality of life.
The SEMECO-IC, implemented in 22nm FDSOI CMOS technology, processes EEG markers of attention and auditory perception to enable real-time neurofeedback and closed-loop system adaptation. This approach allows for the targeted suppression of acoustic distractors, such as competing speakers, thereby reducing cognitive load during social communication. To this end, the architecture uses deep neural networks that incorporate uncertainty estimation. The hardware platform serves as a demonstrator and testbed for next-generation closed-loop neural interfaces.
| Technology | 22 nm FDSOI |
| Area | 2.09 mm² |
| Tape-out | August 2025 |
| Publication | doi.org/10.48550/arXiv.2608.20198 |
SEMECO-IC (Layout)