TwinLab – A Research Collaboration between the Masdar Institute in Abu Dhabi and Technische Universität Dresden
On April 12, 2012, the Abu Dhabi-Saxony Partnership
Committee and a Saxon delegation led by the Chief of the State
Chancellery and State Minister of the Free State of Saxony, Dr.
Johannes Beermann, inaugurated in Abu Dhabi the joint research
project TwinLab between the Masdar Institute in Abu Dhabi and
Technische Universität Dresden. The two research labs of the
TwinLab will carry out research on a topic of economic interest
for the semiconductor industry, namely the design and
manufacturing of 3D chip stacks.
Gerhard Fettweis, Professor and Head of the Vodafone Chair
Mobile Communications Systems at TU Dresden and one of the
founders of the TwinLab has ambitious plans for his project:
“The Lab is to be construed as catalyst for wider and deeper
cooperation in the future. Our TwinLab is the first jointly
established research project of its kind. We hope that our lab
will develop successfully and become a model for other TwinLabs
tackling further challenging research topics of mutual
Today, chips are placed laminary (2D) to build complex
structures which takes up a relatively large area of space.
However, modern applications require even smaller and more
efficient components. Therefore, scientists around Prof.
Gerhard Fettweis and Steve Griffiths (Masdar Institute, Abu
Dhabi) want to build “chip stacks”. Through this
3D-construction principle it will be possible to integrate more
chips per area and to integrate chips of different
semiconductor technologies. Additionally, more sufficient power
usage can be achieved, i.e. energy losses can be reduced
leading to significant energy savings. Another even more import
advantage is the much higher data rate which can be achieved
because the single chips are much closer to each other so that
signals transmitted between them have much shorter ways. In
particular, Through Silicon Vias (TSVs), the electrical
connection between metal and wafer silicon, play a very special
role in 3D chip stacks. The goal is to develop modules (design
blocks) for high-rate interfaces between multiple chips in a
semiconductor chip stack. These interfaces need to be well
adapted to the material properties as well as to the line
routing in the chip stack. To reach this goal, the project will
investigate the interfaces and line routing for high-speed
communication networks in 3D-integrated chips. This includes a
thorough characterization of possible interface techniques
(copper lines, optical wave guides, and wireless coupling),
different semiconductor technologies (SOI, SiGe, etc.) and two
types of TSVs (face-to-face and back-to-face).
Last modified: 20.04.2012 13:33
Author: Pressestelle (Zuständig für die Presseinformationen) expired
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