Semiconductor Technology II

Prof.Dr.rer.nat. J. W. Bartha

Time budget  V/Ü/P:  2/0/1

  • Where and when:
    • Lecture: Thursdays  3. DS, Lecture, GÖR/0226/H
    • Lab: By appointment,  Cleanroom Lab

  • First lecture: Thursday, Apr. 07, 2022

Attention: The lecture will be given via video streams which you access by hyperlinks embedded in the pdf slides to be downloaded from the OPAL learning group folder.

Please register at https://bildungsportal.sachsen.de/opal/auth/RepositoryEntry/5690753028/CourseNode/88474264285906?9

Lecture content

Besides a sufficient inventory of process technologies, the generation of an integrated circuit requires a solig knowledge of the interaction between the device properties and the individual process steps. Effort has to be minimized while performance must be increased. This art named process integration is the major topic of the second part of the course.
Starting with the basic function of a MOS field effect transistor, we will develop simple structures of integrated circuits and always focus on the interaction of device performance and manufacturing technology. Concepts of self alignment as well as parasitic effects will be explained. Finally we will run through the whole process sequence for the fabrication of a CMOS product.

Laboratory

Opal: https://bildungsportal.sachsen.de/opal/auth/RepositoryEntry/5690753028/CourseNode/101358303504194?3

Within the laboratory term of the lecture the students will go through the process steps to make a two layer wiring structure, which will be finally electrically qualified. The processing contains:

  • PECVD
  • RIE
  • PVD
  • Lithography
  • Electrochemical Deposition

Attention: The lab is an own course. If you want to attend the lab as well, please sign up extra for "Semiconductor Techn. 2 (SS) Lab" in the OPAL

Open to PhD students as well!

Lecture slides (download)

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Philipp Wenskus
Letzte Änderung: 17.03.2022