Performance and energy efficiency analysis for innovative computer architectures

© Joseph Schuchart

Although high performance computers become more and more powerful, especially in terms of their theoretical peak performance, achieving best performance for scientific applications requires a detailed understanding of the architecture and performance of the underlying computing systems. In addition to conducting detailed studies of the function and performance of new processor architectures and memory hierarchies, ZIH is actively developing benchmark environments to facilitate such research and to significantly improve the understanding of the hardware behavior in research and teaching.

Another essential focus along this area of research is the energy efficiency of computer systems. With the decreasing efficiency gains through improved manufacturing processes, a broader approach is necessary. The performance optimization of parallel applications is promising in terms of energy efficiency, particularly through intelligent control (within the scientific applications) of the underlying hardware.

In terms of novel computer architectures, another research focus concerns the hardware accelerators, in the present mainly represented by general purpose GPUs (GPGPUs) and many-core processors. The research at ZIH in this area ranges from the detailed study of hardware accelerators, to the development of software tools for performance analysis, and to porting and optimizing scientific applications on accelerator architectures.

Current Projects

• FIRESTARTER: A processor stress test utility
• lo2s: lightweight Linux performance monitoring
• HDEEM: High Definition Energy Efficiency Monitoring
• Dresden GPU Center of Excellence
• cfAED: Center For Advancing Electronics Dresden
• BenchIT: Flexible and portable performance analysis for computer systems
• SPEC: Standard Performance Evaluation Cooperation

Completed Projects

• READEX: Runtime Exploitation of Application Dynamism for Energy-Efficient Exascale Computing
• HAEC: Highly Adaptive Energy Efficient Computing
• HI-CFD / Scout: Highly efficient implementation of CFD codes for HPC many-core architectures

• Score-E: Scalable Tools for the Analysis and Optimization of Energy Consumption in HPC

• Cool Silicon: Energy Efficiency Innovations from Silicon Saxony
• GASPI: Global Address Space Programming Interface
• SIOX: Scalable I/O for Extreme Performance
• eeClust: Energy-efficient cluster computing
• Fast Matrix Multiplication on Cell (SMP) Systems
• Software Tracing on Cell/B.E. Processors
• EP-Cache
• PARbench

Contact

© Robert Gommlich

Name

Dr. Daniel Hackenberg

Deputy Director / Group leader Energy Efficiency

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Organization Name

Center for Information Services and High Performance Computing (ZIH)

Center for Information Services and High Performance Computing (ZIH)

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Willers-Bau, Room A 204 Zellescher Weg 12

01069 Dresden

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+49 351 463-37773

Selected Publications

• Thomas Ilsche, Mario Bielert, Christian von Elm. "Bridging the Gap between Application Performance Analysis and System Monitoring" In: International Conference on Cluster Computing (CLUSTER), 2022. DOI: 10.1109/CLUSTER51413.2022.00080

• Markus Velten,Robert Schöne,Thomas Ilsche,Daniel Hackenberg, "Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors" In:
  International Conference on Performance Engineering (ICPE), 2022. DOI: 10.1145/3489525.3511689

• Andreas Gocht, Robert Schöne, Mario Bielert, "Q-Learning Inspired Self-Tuning for Energy Efficiency in HPC" In: International Conference on High Performance Computing & Simulation (HPCS), 2019. DOI: 10.1109/HPCS48598.2019.9188112

• Robert Schöne, Thomas Ilsche, Mario Bielert, Markus Velten, Markus Schmidl, Daniel Hackenberg. "Energy Efficiency Aspects of the AMD Zen 2 Architecture" In: Energy Efficient HPC State of the Practice Workshop (in conjunction with IEEE Cluster). 2021. DOI: 10.1109/Cluster48925.2021.00087

• Robert Schöne, Markus Schmidl, Mario Bielert, Daniel Hackenberg. "FIRESTARTER 2: Dynamic Code Generation for Processor Stress Tests". In: Energy Efficient HPC State of the Practice Workshop (in conjunction with IEEE Cluster). 2021. DOI: 10.1109/Cluster48925.2021.00084

• Thomas Ilsche, Daniel Hackenberg, Robert Schöne, Mario Bielert, Franz Höpfner and Wolfgang E. Nagel. "MetricQ: A Scalable Infrastructure for Processing High-Resolution Time Series Data" In: 2019 IEEE/ACM Industry/University Joint International Workshop on Data-center Automation, Analytics, and Control (DAAC). 2019. DOI: 10.1109/DAAC49578.2019.00007

• Robert Schöne, Thomas Ilsche, Mario Bielert, Andreas Gocht, Daniel Hackenberg. "Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance" In: 6th Special Session on High Performance Computing Benchmarking and Optimization (HPBench). 2019. DOI: 10.1109/HPCS48598.2019.9188239

• Daniel Molka, Robert Schöne, Daniel Hackenberg, Wolfgang E. Nagel. "Detecting Memory-Boundedness with Hardware Performance Counters", In: International Conference on Performance Engineering (ICPE), 2017. DOI: 10.1145/3030207.3030223

• Thomas Ilsche, Robert Schöne, Joseph Schuchart, Daniel Hackenberg, Marc Simon, Yiannis Georgiou and Wolfgang E. Nagel. "Power Measurement Techniques for Energy-Efficient Computing: Reconciling Scalability, Resolution, and Accuracy" In: Second Workshop on Energy-Aware High Performance Computing (EnA-HPC). 2017. DOI: 10.1007/s00450-018-0392-9 

• Thomas Ilsche, Robert Schöne, Mario Bielert, Andreas Gocht and Daniel Hackenberg. "lo2s – Multi-Core System and Application Performance Analysis for Linux" In: Workshop on Monitoring and Analysis for High Performance Computing Systems Plus Applications (HPCMASPA). 2017. DOI: 10.1109/CLUSTER.2017.116
• Thomas Ilsche, Marcus Hähnel, Robert Schöne, Mario Bielert and Daniel Hackenberg. "Powernightmares: The Challenge of Efficiently Using Sleep States on Multi-Core Systems" In: 5th Workshop on Runtime and Operating Systems for the Many-core Era (ROME). 2017. https://doi.org/10.1007/978-3-319-75178-8_50
• Robert Schöne, Thomas Ilsche, Mario Bielert, Daniel Molka, Daniel Hackenberg. "Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors" In: 4th International Workshop on Energy Efficient Supercomputing (E2SC). 2016. DOI: doi.org/10.1109/E2SC.2016.015

• Joseph Schuchart, Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Ramkumar Nagappan, Michael K. Patterson. “The Shift from Processor Power Consumption to Performance Variations: Fundamental Implications at Scale” In: First Workshop on Energy-Aware High Performance Computing (EnA-HPC). 2016. DOI: 10.1007/s00450-016-0327-2 

• R. Schöne, R. Tschüter, T. Ilsche, J. Schuchart, D. Hackenberg, and W.  E. Nagel. “Extending the Functionality of Score-P through Plugins:  Interfaces and Use Cases” In: Tools for High Performance Computing 2016,  DOI: 10.1007/978-3-319-56702-0_4

• Mario Bielert, Florina M. Ciorba, Kim Feldhoff, Thomas Ilsche, and Wolfgang E. Nagel. “HAEC-SIM: A Simulation Framework for Highly Adaptive Energy-Efficient Computing Platforms.” In: Eighth Conference on Simulation Tools and Techniques. 2015. DOI: 10.4108/eai.24-8-2015.2261105
• Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Daniel Molka, Joseph Schuchart, and Robin Geyer: " An Energy Efficiency Feature Survey of the Intel Haswell Processor" In: 2015 IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW). DOI: 10.1109/IPDPSW.2015.70
• Thomas Ilsche, Daniel Hackenberg, Stefan Graul, Joseph Schuchart, and Robert Schöne. “Power Measurements for Compute Nodes: Improving Sampling Rates, Granularity, and Accuracy” In: Sixth International Green Computing Conference and Sustainable Computing Conference (IGSC). 2015. DOI: 10.1109/IGCC.2015.7393710
• Daniel Molka, Daniel Hackenberg, Robert Schöne, Wolfgang E. Nagel “Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture”, Proceedings of the 44th International Conference on Parallel Processing (ICPP'15), IEEE, 2015
• Daniel Hackenberg, Thomas Ilsche, Joseph Schuchart, Robert Schöne, Wolfgang E. Nagel, Marc Simon, and Yiannis Georgiou. HDEEM: High Definition Energy Efficiency Monitoring. In: Proceedings of the 2nd International Workshop on Energy Efficient Supercomputing (E2SC). 2014. DOI: 10.1109/E2SC.2014.13
• Daniel Molka, Daniel Hackenberg, Robert Schöne, “Main Memory and Cache Performance of Intel Sandy Bridge and AMD Bulldozer”, In Proceedings of the 2014 ACM SIGPLAN workshop on Memory Systems Performance and Correctness (MSPC'14), ACM, 2014
• D. Hackenberg, T. Ilsche, R. Schoene, D. Molka, M. Schmidt, and W. E. Nagel: Power Measurement Techniques on Standard Compute Nodes: A Quantitative Comparison. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS13), Austin, TX USA, April 21-23, 2013.
• R. Schöne, D. Hackenberg, D. Molka, “Memory performance at reduced CPU clock speeds: an analysis of current x86_64 processors”, In Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems (HotPower'12), October 7, 2012, Hollywood, USA
• R. Schöne, D. Hackenberg, D. Molka, “Simultaneous Multithreading on x86_64 Systems: An Energy Efficiency Evaluation”, In Procedings of the 4th Workshop on Power-Aware Computing and Systems (HotPower'11), October 23-26, 2011, Cascais, Portugal
• D. Molka, R. Schöne, D. Hackenberg, M. S. Müller, “Memory Performance and SPEC OpenMP Scalability on Quad-Socket x86 64 Systems”, In Procedings of the 11th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP'11), October 24-26 2011, Melbourne, Australia
• D. Molka, D. Hackenberg, R. Schöne and M. S. Müller, “Characterizing the Energy Consumption of Data Transfers and Arithmetic Operations on x86-64 Processors”, In Proceedings of the 1st International Green Computing Conference (IGCC'10), pages 123-133, IEEE, 2010
• D. Hackenberg, D. Molka and W. E. Nagel, “Comparing Cache Architectures and Coherency Protocols on x86-64 Multicore SMP Systems”, In Proceedings of the 42nd International Symposium on Microarchitecture (MICRO'09), pages 413-422, ACM, 2009
• D. Molka, D. Hackenberg, R. Schöne and M. S. Müller, “Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System”, In Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT'09), pages 261-270, IEEE, 2009
• Daniel Hackenberg, Robert Schöne, Wolfgang E Nagel, Stefan Pflüger, Optimizing OpenMP parallelized DGEMM calls on SGI Altix 3700, Lecture Notes in Computer Science for Euro-Par 2006 Parallel Processing, pages 145-154, Januar 01 2006, http://dx.doi.org/10.1007/11823285_15
• Guido Juckeland, Michael Kluge, Wolfgang E. Nagel and Stefan Pflüger, Performance analysis with BenchIT: portable, flexible, easy to use, in: 1st International Conference on Quantitative Evaluation of Systems (QEST 2004), Proceedings, pages 320--321, IEEE Computer Society, 2004